pxa2xx_timer: change info struct name to comply with guidelines
It should be PXA2xxTimerInfo, not pxa2xx_timer_info. Replace all occurences of old name with the new one. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
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@ -89,11 +89,11 @@ typedef struct {
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uint32_t irq_enabled;
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uint32_t reset3;
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uint32_t snapshot;
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} pxa2xx_timer_info;
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} PXA2xxTimerInfo;
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static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
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{
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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int i;
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uint32_t now_vm;
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uint64_t new_qemu;
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@ -110,7 +110,7 @@ static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
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static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
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{
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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uint32_t now_vm;
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uint64_t new_qemu;
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static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
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@ -137,7 +137,7 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
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static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
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{
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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int tm = 0;
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switch (offset) {
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@ -216,7 +216,7 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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int i, tm = 0;
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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switch (offset) {
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case OSMR3: tm ++;
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@ -334,7 +334,7 @@ static CPUWriteMemoryFunc * const pxa2xx_timer_writefn[] = {
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static void pxa2xx_timer_tick(void *opaque)
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{
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PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
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pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
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PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->info;
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if (i->irq_enabled & (1 << t->num)) {
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t->level = 1;
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@ -352,7 +352,7 @@ static void pxa2xx_timer_tick(void *opaque)
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static void pxa2xx_timer_tick4(void *opaque)
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{
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PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
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pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info;
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PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;
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pxa2xx_timer_tick(&t->tm);
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if (t->control & (1 << 3))
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@ -363,7 +363,7 @@ static void pxa2xx_timer_tick4(void *opaque)
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static void pxa2xx_timer_save(QEMUFile *f, void *opaque)
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{
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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int i;
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qemu_put_be32s(f, (uint32_t *) &s->clock);
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@ -393,7 +393,7 @@ static void pxa2xx_timer_save(QEMUFile *f, void *opaque)
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static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id)
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{
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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int64_t now;
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int i;
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@ -428,14 +428,14 @@ static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id)
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return 0;
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}
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static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
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static PXA2xxTimerInfo *pxa2xx_timer_init(target_phys_addr_t base,
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DeviceState *pic)
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{
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int i;
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int iomemtype;
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pxa2xx_timer_info *s;
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PXA2xxTimerInfo *s;
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s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
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s = (PXA2xxTimerInfo *) qemu_mallocz(sizeof(PXA2xxTimerInfo));
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s->irq_enabled = 0;
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s->oldclock = 0;
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s->clock = 0;
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@ -464,14 +464,14 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
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void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic)
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{
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pxa2xx_timer_info *s = pxa2xx_timer_init(base, pic);
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PXA2xxTimerInfo *s = pxa2xx_timer_init(base, pic);
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s->freq = PXA25X_FREQ;
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s->tm4 = NULL;
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}
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void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic)
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{
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pxa2xx_timer_info *s = pxa2xx_timer_init(base, pic);
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PXA2xxTimerInfo *s = pxa2xx_timer_init(base, pic);
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int i;
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s->freq = PXA27X_FREQ;
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s->tm4 = (PXA2xxTimer4 *) qemu_mallocz(8 *
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