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target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s

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Do not depend on the RVD extension, take input and output via
TCGv_i64 instead of fpu regno.  Move the function to translate.c
so that it can be used in multiple trans_*.inc.c files.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2020-07-23 17:28:02 -07:00 committed by Alistair Francis
parent 9921e3d330
commit d36a86d01e
2 changed files with 12 additions and 15 deletions
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16
target/riscv/insn_trans/trans_rvf.c.inc
View file

@ -23,20 +23,6 @@
return false; \
} while (0)
/*
* RISC-V requires NaN-boxing of narrower width floating
* point values. This applies when a 32-bit value is
* assigned to a 64-bit FP register. Thus this does not
* apply when the RVD extension is not present.
*/
static void gen_nanbox_fpr(DisasContext *ctx, int regno)
{
if (has_ext(ctx, RVD)) {
tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno],
MAKE_64BIT_MASK(32, 32));
}
}
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
TCGv t0 = tcg_temp_new();
@ -46,7 +32,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
gen_nanbox_fpr(ctx, a->rd);
gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
tcg_temp_free(t0);
mark_fs_dirty(ctx);

11
target/riscv/translate.c
View file

@ -90,6 +90,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa & ext;
}
/*
* RISC-V requires NaN-boxing of narrower width floating point values.
* This applies when a 32-bit value is assigned to a 64-bit FP register.
* For consistency and simplicity, we nanbox results even when the RVD
* extension is not present.
*/
static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
{
tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
}
static void generate_exception(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);