target/arm: Apply TBI to ESR_ELx in helper_exception_return
We missed this case within AArch64.ExceptionReturn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200302175829.2183-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1031,6 +1031,8 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
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"AArch32 EL%d PC 0x%" PRIx32 "\n",
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cur_el, new_el, env->regs[15]);
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} else {
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int tbii;
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env->aarch64 = 1;
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spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar);
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pstate_write(env, spsr);
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@ -1038,8 +1040,27 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
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env->pstate &= ~PSTATE_SS;
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}
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aarch64_restore_sp(env, new_el);
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env->pc = new_pc;
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helper_rebuild_hflags_a64(env, new_el);
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/*
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* Apply TBI to the exception return address. We had to delay this
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* until after we selected the new EL, so that we could select the
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* correct TBI+TBID bits. This is made easier by waiting until after
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* the hflags rebuild, since we can pull the composite TBII field
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* from there.
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*/
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tbii = FIELD_EX32(env->hflags, TBFLAG_A64, TBII);
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if ((tbii >> extract64(new_pc, 55, 1)) & 1) {
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/* TBI is enabled. */
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int core_mmu_idx = cpu_mmu_index(env, false);
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if (regime_has_2_ranges(core_to_aa64_mmu_idx(core_mmu_idx))) {
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new_pc = sextract64(new_pc, 0, 56);
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} else {
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new_pc = extract64(new_pc, 0, 56);
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}
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}
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env->pc = new_pc;
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qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
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"AArch64 EL%d PC 0x%" PRIx64 "\n",
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cur_el, new_el, env->pc);
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