target/microblaze: Convert to DisasContextBase
Part one of conversion to the generic translator_loop is to use the DisasContextBase and the members therein. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
0b46fa0821
commit
d4705ae084
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@ -67,8 +67,8 @@ static TCGv_i32 cpu_res_val;
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/* This is the state at translation time. */
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typedef struct DisasContext {
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DisasContextBase base;
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MicroBlazeCPU *cpu;
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uint32_t pc;
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/* Decoder. */
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int type_b;
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@ -81,7 +81,6 @@ typedef struct DisasContext {
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unsigned int delayed_branch;
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unsigned int tb_flags, synced_flags; /* tb dependent flags. */
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unsigned int clear_imm;
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int is_jmp;
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#define JMP_NOJMP 0
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#define JMP_DIRECT 1
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@ -91,8 +90,6 @@ typedef struct DisasContext {
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uint32_t jmp_pc;
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int abort_at_next_insn;
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struct TranslationBlock *tb;
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int singlestep_enabled;
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} DisasContext;
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static inline void t_sync_flags(DisasContext *dc)
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@ -110,13 +107,13 @@ static void gen_raise_exception(DisasContext *dc, uint32_t index)
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gen_helper_raise_exception(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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dc->is_jmp = DISAS_NORETURN;
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dc->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_raise_exception_sync(DisasContext *dc, uint32_t index)
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{
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t_sync_flags(dc);
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
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gen_raise_exception(dc, index);
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}
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@ -132,7 +129,7 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
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static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
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{
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#ifndef CONFIG_USER_ONLY
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return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
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return (dc->base.pc_first & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
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#else
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return true;
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#endif
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@ -140,7 +137,7 @@ static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
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static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
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{
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if (dc->singlestep_enabled) {
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if (dc->base.singlestep_enabled) {
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TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
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tcg_gen_movi_i32(cpu_pc, dest);
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gen_helper_raise_exception(cpu_env, tmp);
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@ -148,12 +145,12 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
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} else if (use_goto_tb(dc, dest)) {
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tcg_gen_goto_tb(n);
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tcg_gen_movi_i32(cpu_pc, dest);
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tcg_gen_exit_tb(dc->tb, n);
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tcg_gen_exit_tb(dc->base.tb, n);
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} else {
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tcg_gen_movi_i32(cpu_pc, dest);
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tcg_gen_exit_tb(NULL, 0);
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}
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dc->is_jmp = DISAS_NORETURN;
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dc->base.is_jmp = DISAS_NORETURN;
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}
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/*
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@ -468,8 +465,8 @@ static void dec_msr(DisasContext *dc)
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msr_write(dc, t0);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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tcg_gen_movi_i32(cpu_pc, dc->pc + 4);
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dc->is_jmp = DISAS_UPDATE;
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tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4);
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dc->base.is_jmp = DISAS_UPDATE;
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return;
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}
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@ -546,7 +543,7 @@ static void dec_msr(DisasContext *dc)
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switch (sr) {
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case SR_PC:
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tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc);
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tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next);
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break;
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case SR_MSR:
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msr_read(dc, cpu_R[dc->rd]);
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@ -813,7 +810,7 @@ static void dec_bit(DisasContext *dc)
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break;
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default:
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cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
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dc->pc, op, dc->rd, dc->ra, dc->rb);
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(uint32_t)dc->base.pc_next, op, dc->rd, dc->ra, dc->rb);
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break;
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}
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}
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@ -994,7 +991,7 @@ static void dec_load(DisasContext *dc)
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TCGv_i32 treg = tcg_const_i32(dc->rd);
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TCGv_i32 tsize = tcg_const_i32(size - 1);
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
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gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
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tcg_temp_free_i32(t0);
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@ -1114,7 +1111,7 @@ static void dec_store(DisasContext *dc)
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TCGv_i32 treg = tcg_const_i32(dc->rd);
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TCGv_i32 tsize = tcg_const_i32(size - 1);
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
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/* FIXME: if the alignment is wrong, we should restore the value
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* in memory. One possible way to achieve this is to probe
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* the MMU prior to the memaccess, thay way we could put
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@ -1201,12 +1198,12 @@ static void dec_bcc(DisasContext *dc)
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if (dec_alu_op_b_is_small_imm(dc)) {
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int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
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tcg_gen_movi_i32(cpu_btarget, dc->pc + offset);
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tcg_gen_movi_i32(cpu_btarget, dc->base.pc_next + offset);
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dc->jmp = JMP_DIRECT_CC;
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dc->jmp_pc = dc->pc + offset;
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dc->jmp_pc = dc->base.pc_next + offset;
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} else {
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dc->jmp = JMP_INDIRECT;
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tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc);
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tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next);
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}
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eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]);
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}
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@ -1250,7 +1247,7 @@ static void dec_br(DisasContext *dc)
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+offsetof(CPUState, halted));
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tcg_temp_free_i32(tmp_1);
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tcg_gen_movi_i32(cpu_pc, dc->pc + 4);
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tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4);
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gen_raise_exception(dc, EXCP_HLT);
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return;
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@ -1270,7 +1267,7 @@ static void dec_br(DisasContext *dc)
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dec_setup_dslot(dc);
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}
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if (link && dc->rd)
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tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc);
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tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next);
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dc->jmp = JMP_INDIRECT;
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if (abs) {
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@ -1291,10 +1288,10 @@ static void dec_br(DisasContext *dc)
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} else {
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if (dec_alu_op_b_is_small_imm(dc)) {
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dc->jmp = JMP_DIRECT;
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dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
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dc->jmp_pc = dc->base.pc_next + (int32_t)((int16_t)dc->imm);
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} else {
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tcg_gen_movi_i32(cpu_btaken, 1);
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tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc);
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tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next);
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}
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}
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}
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@ -1459,7 +1456,8 @@ static void dec_fpu(DisasContext *dc)
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qemu_log_mask(LOG_UNIMP,
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"unimplemented fcmp fpu_insn=%x pc=%x"
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" opc=%x\n",
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fpu_insn, dc->pc, dc->opcode);
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fpu_insn, (uint32_t)dc->base.pc_next,
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dc->opcode);
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dc->abort_at_next_insn = 1;
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break;
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}
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@ -1489,7 +1487,7 @@ static void dec_fpu(DisasContext *dc)
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default:
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qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x"
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" opc=%x\n",
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fpu_insn, dc->pc, dc->opcode);
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fpu_insn, (uint32_t)dc->base.pc_next, dc->opcode);
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dc->abort_at_next_insn = 1;
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break;
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}
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@ -1500,7 +1498,8 @@ static void dec_null(DisasContext *dc)
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if (trap_illegal(dc, true)) {
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return;
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}
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qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
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qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n",
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(uint32_t)dc->base.pc_next, dc->opcode);
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dc->abort_at_next_insn = 1;
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}
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@ -1610,19 +1609,20 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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pc_start = tb->pc;
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dc->cpu = cpu;
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dc->tb = tb;
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org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
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dc->is_jmp = DISAS_NEXT;
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dc->jmp = 0;
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dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
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if (dc->delayed_branch) {
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dc->jmp = JMP_INDIRECT;
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}
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dc->pc = pc_start;
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dc->singlestep_enabled = cs->singlestep_enabled;
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dc->base.pc_first = pc_start;
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dc->base.pc_next = pc_start;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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dc->cpustate_changed = 0;
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dc->abort_at_next_insn = 0;
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dc->base.is_jmp = DISAS_NEXT;
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dc->base.tb = tb;
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if (pc_start & 3) {
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cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
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@ -1634,31 +1634,31 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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gen_tb_start(tb);
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do
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{
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tcg_gen_insn_start(dc->pc);
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tcg_gen_insn_start(dc->base.pc_next);
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num_insns++;
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if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
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if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) {
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gen_raise_exception_sync(dc, EXCP_DEBUG);
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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dc->pc += 4;
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dc->base.pc_next += 4;
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break;
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}
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/* Pretty disas. */
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LOG_DIS("%8.8x:\t", dc->pc);
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LOG_DIS("%8.8x:\t", (uint32_t)dc->base.pc_next);
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if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
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gen_io_start();
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}
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dc->clear_imm = 1;
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decode(dc, cpu_ldl_code(env, dc->pc));
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decode(dc, cpu_ldl_code(env, dc->base.pc_next));
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if (dc->clear_imm)
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dc->tb_flags &= ~IMM_FLAG;
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dc->pc += 4;
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dc->base.pc_next += 4;
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if (dc->delayed_branch) {
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dc->delayed_branch--;
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@ -1673,10 +1673,10 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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dc->tb_flags &= ~D_FLAG;
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/* If it is a direct jump, try direct chaining. */
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if (dc->jmp == JMP_INDIRECT) {
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TCGv_i32 tmp_pc = tcg_const_i32(dc->pc);
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TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next);
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eval_cond_jmp(dc, cpu_btarget, tmp_pc);
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tcg_temp_free_i32(tmp_pc);
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dc->is_jmp = DISAS_JUMP;
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dc->base.is_jmp = DISAS_JUMP;
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} else if (dc->jmp == JMP_DIRECT) {
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t_sync_flags(dc);
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gen_goto_tb(dc, 0, dc->jmp_pc);
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@ -1685,26 +1685,26 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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t_sync_flags(dc);
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/* Conditional jmp. */
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tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1);
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gen_goto_tb(dc, 1, dc->pc);
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gen_goto_tb(dc, 1, dc->base.pc_next);
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gen_set_label(l1);
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gen_goto_tb(dc, 0, dc->jmp_pc);
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}
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break;
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}
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}
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if (cs->singlestep_enabled) {
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if (dc->base.singlestep_enabled) {
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break;
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}
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} while (!dc->is_jmp && !dc->cpustate_changed
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} while (!dc->base.is_jmp && !dc->cpustate_changed
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&& !tcg_op_buf_full()
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&& !singlestep
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&& (dc->pc - page_start < TARGET_PAGE_SIZE)
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&& (dc->base.pc_next - page_start < TARGET_PAGE_SIZE)
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&& num_insns < max_insns);
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npc = dc->pc;
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npc = dc->base.pc_next;
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if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
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if (dc->tb_flags & D_FLAG) {
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dc->is_jmp = DISAS_UPDATE;
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dc->base.is_jmp = DISAS_UPDATE;
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tcg_gen_movi_i32(cpu_pc, npc);
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sync_jmpstate(dc);
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} else
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@ -1712,25 +1712,25 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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}
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/* Force an update if the per-tb cpu state has changed. */
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if (dc->is_jmp == DISAS_NEXT
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if (dc->base.is_jmp == DISAS_NEXT
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&& (dc->cpustate_changed || org_flags != dc->tb_flags)) {
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dc->is_jmp = DISAS_UPDATE;
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dc->base.is_jmp = DISAS_UPDATE;
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tcg_gen_movi_i32(cpu_pc, npc);
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}
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t_sync_flags(dc);
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if (dc->is_jmp == DISAS_NORETURN) {
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if (dc->base.is_jmp == DISAS_NORETURN) {
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/* nothing more to generate */
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} else if (unlikely(cs->singlestep_enabled)) {
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TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
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if (dc->is_jmp != DISAS_JUMP) {
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if (dc->base.is_jmp != DISAS_JUMP) {
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tcg_gen_movi_i32(cpu_pc, npc);
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}
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gen_helper_raise_exception(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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} else {
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switch(dc->is_jmp) {
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switch (dc->base.is_jmp) {
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case DISAS_NEXT:
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gen_goto_tb(dc, 1, npc);
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break;
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@ -1746,7 +1746,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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}
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gen_tb_end(tb, num_insns);
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tb->size = dc->pc - pc_start;
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tb->size = dc->base.pc_next - pc_start;
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tb->icount = num_insns;
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#ifdef DEBUG_DISAS
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@ -1755,7 +1755,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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&& qemu_log_in_addr_range(pc_start)) {
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FILE *logfile = qemu_log_lock();
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qemu_log("--------------\n");
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log_target_disas(cs, pc_start, dc->pc - pc_start);
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log_target_disas(cs, pc_start, dc->base.pc_next - pc_start);
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qemu_log_unlock(logfile);
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}
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#endif
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