target-sparc: Tidy do_branch interfaces
We always pass cpu_cond to the r_cond parameter. Use that global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -1337,8 +1337,7 @@ static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
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}
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}
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#endif
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#endif
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static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
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static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
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TCGv r_cond)
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{
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{
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unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
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unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
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target_ulong target = dc->pc + offset;
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target_ulong target = dc->pc + offset;
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@ -1368,10 +1367,10 @@ static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
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tcg_gen_mov_tl(cpu_pc, cpu_npc);
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tcg_gen_mov_tl(cpu_pc, cpu_npc);
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}
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}
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} else {
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} else {
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flush_cond(dc, r_cond);
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flush_cond(dc, cpu_cond);
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gen_cond(r_cond, cc, cond, dc);
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gen_cond(cpu_cond, cc, cond, dc);
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if (a) {
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if (a) {
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gen_branch_a(dc, target, dc->npc, r_cond);
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gen_branch_a(dc, target, dc->npc, cpu_cond);
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dc->is_br = 1;
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dc->is_br = 1;
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} else {
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} else {
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dc->pc = dc->npc;
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dc->pc = dc->npc;
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@ -1387,8 +1386,7 @@ static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
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}
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}
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}
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}
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static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
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static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
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TCGv r_cond)
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{
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{
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unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
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unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
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target_ulong target = dc->pc + offset;
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target_ulong target = dc->pc + offset;
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@ -1418,10 +1416,10 @@ static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
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tcg_gen_mov_tl(cpu_pc, cpu_npc);
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tcg_gen_mov_tl(cpu_pc, cpu_npc);
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}
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}
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} else {
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} else {
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flush_cond(dc, r_cond);
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flush_cond(dc, cpu_cond);
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gen_fcond(r_cond, cc, cond);
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gen_fcond(cpu_cond, cc, cond);
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if (a) {
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if (a) {
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gen_branch_a(dc, target, dc->npc, r_cond);
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gen_branch_a(dc, target, dc->npc, cpu_cond);
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dc->is_br = 1;
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dc->is_br = 1;
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} else {
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} else {
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dc->pc = dc->npc;
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dc->pc = dc->npc;
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@ -1439,7 +1437,7 @@ static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
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#ifdef TARGET_SPARC64
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#ifdef TARGET_SPARC64
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static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
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static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
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TCGv r_cond, TCGv r_reg)
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TCGv r_reg)
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{
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{
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unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
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unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
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target_ulong target = dc->pc + offset;
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target_ulong target = dc->pc + offset;
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@ -1447,10 +1445,10 @@ static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
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if (unlikely(AM_CHECK(dc))) {
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if (unlikely(AM_CHECK(dc))) {
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target &= 0xffffffffULL;
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target &= 0xffffffffULL;
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}
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}
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flush_cond(dc, r_cond);
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flush_cond(dc, cpu_cond);
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gen_cond_reg(r_cond, cond, r_reg);
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gen_cond_reg(cpu_cond, cond, r_reg);
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if (a) {
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if (a) {
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gen_branch_a(dc, target, dc->npc, r_cond);
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gen_branch_a(dc, target, dc->npc, cpu_cond);
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dc->is_br = 1;
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dc->is_br = 1;
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} else {
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} else {
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dc->pc = dc->npc;
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dc->pc = dc->npc;
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@ -2421,9 +2419,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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target <<= 2;
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target <<= 2;
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cc = GET_FIELD_SP(insn, 20, 21);
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cc = GET_FIELD_SP(insn, 20, 21);
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if (cc == 0)
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if (cc == 0)
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do_branch(dc, target, insn, 0, cpu_cond);
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do_branch(dc, target, insn, 0);
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else if (cc == 2)
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else if (cc == 2)
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do_branch(dc, target, insn, 1, cpu_cond);
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do_branch(dc, target, insn, 1);
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else
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else
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goto illegal_insn;
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goto illegal_insn;
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goto jmp_insn;
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goto jmp_insn;
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@ -2435,7 +2433,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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target = sign_extend(target, 16);
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target = sign_extend(target, 16);
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target <<= 2;
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target <<= 2;
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cpu_src1 = get_src1(insn, cpu_src1);
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cpu_src1 = get_src1(insn, cpu_src1);
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do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
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do_branch_reg(dc, target, insn, cpu_src1);
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goto jmp_insn;
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goto jmp_insn;
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}
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}
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case 0x5: /* V9 FBPcc */
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case 0x5: /* V9 FBPcc */
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@ -2446,7 +2444,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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target = GET_FIELD_SP(insn, 0, 18);
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target = GET_FIELD_SP(insn, 0, 18);
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target = sign_extend(target, 19);
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target = sign_extend(target, 19);
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target <<= 2;
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target <<= 2;
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do_fbranch(dc, target, insn, cc, cpu_cond);
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do_fbranch(dc, target, insn, cc);
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goto jmp_insn;
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goto jmp_insn;
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}
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}
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#else
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#else
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@ -2460,7 +2458,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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target = GET_FIELD(insn, 10, 31);
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target = GET_FIELD(insn, 10, 31);
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target = sign_extend(target, 22);
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target = sign_extend(target, 22);
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target <<= 2;
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target <<= 2;
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do_branch(dc, target, insn, 0, cpu_cond);
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do_branch(dc, target, insn, 0);
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goto jmp_insn;
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goto jmp_insn;
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}
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}
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case 0x6: /* FBN+x */
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case 0x6: /* FBN+x */
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@ -2470,7 +2468,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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target = GET_FIELD(insn, 10, 31);
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target = GET_FIELD(insn, 10, 31);
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target = sign_extend(target, 22);
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target = sign_extend(target, 22);
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target <<= 2;
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target <<= 2;
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do_fbranch(dc, target, insn, 0, cpu_cond);
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do_fbranch(dc, target, insn, 0);
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goto jmp_insn;
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goto jmp_insn;
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}
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}
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case 0x4: /* SETHI */
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case 0x4: /* SETHI */
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