target/arm: Split out rebuild_hflags_a64
Create a function to compute the values of the TBFLAG_A64 bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Note that not all BTI related flags are cached, so we have to test the BTI feature twice -- once for those bits moved out to rebuild_hflags_a64 and once for those bits that remain in cpu_get_tb_cpu_state. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -11070,6 +11070,71 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
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return flags;
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}
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static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
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ARMMMUIdx mmu_idx)
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{
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ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
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ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
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uint32_t flags = 0;
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uint64_t sctlr;
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int tbii, tbid;
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flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
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/* FIXME: ARMv8.1-VHE S2 translation regime. */
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if (regime_el(env, stage1) < 2) {
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ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
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tbid = (p1.tbi << 1) | p0.tbi;
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tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
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} else {
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tbid = p0.tbi;
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tbii = tbid & !p0.tbid;
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}
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flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
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flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);
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if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
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int sve_el = sve_exception_el(env, el);
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uint32_t zcr_len;
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/*
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* If SVE is disabled, but FP is enabled,
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* then the effective len is 0.
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*/
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if (sve_el != 0 && fp_el == 0) {
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zcr_len = 0;
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} else {
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zcr_len = sve_zcr_len_for_el(env, el);
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}
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flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
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flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
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}
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sctlr = arm_sctlr(env, el);
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if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
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/*
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* In order to save space in flags, we record only whether
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* pauth is "inactive", meaning all insns are implemented as
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* a nop, or "active" when some action must be performed.
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* The decision of which action to take is left to a helper.
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*/
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if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
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flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
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}
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}
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if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
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/* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
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if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
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flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
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}
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}
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return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
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}
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void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *pflags)
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{
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@ -11079,67 +11144,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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uint32_t flags = 0;
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if (is_a64(env)) {
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ARMCPU *cpu = env_archcpu(env);
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uint64_t sctlr;
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*pc = env->pc;
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flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
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/* Get control bits for tagged addresses. */
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{
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ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
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ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
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int tbii, tbid;
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/* FIXME: ARMv8.1-VHE S2 translation regime. */
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if (regime_el(env, stage1) < 2) {
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ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
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tbid = (p1.tbi << 1) | p0.tbi;
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tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
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} else {
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tbid = p0.tbi;
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tbii = tbid & !p0.tbid;
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}
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flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
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flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);
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}
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if (cpu_isar_feature(aa64_sve, cpu)) {
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int sve_el = sve_exception_el(env, current_el);
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uint32_t zcr_len;
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/* If SVE is disabled, but FP is enabled,
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* then the effective len is 0.
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*/
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if (sve_el != 0 && fp_el == 0) {
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zcr_len = 0;
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} else {
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zcr_len = sve_zcr_len_for_el(env, current_el);
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}
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flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
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flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
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}
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sctlr = arm_sctlr(env, current_el);
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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/*
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* In order to save space in flags, we record only whether
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* pauth is "inactive", meaning all insns are implemented as
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* a nop, or "active" when some action must be performed.
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* The decision of which action to take is left to a helper.
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*/
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if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
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flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
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}
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}
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if (cpu_isar_feature(aa64_bti, cpu)) {
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/* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
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if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
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flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
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}
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flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx);
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if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
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flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
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}
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} else {
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@ -11159,9 +11166,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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flags = FIELD_DP32(flags, TBFLAG_A32,
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XSCALE_CPAR, env->cp15.c15_cpar);
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}
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}
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flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags);
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flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags);
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}
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/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
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* states defined in the ARM ARM for software singlestep:
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