ppc/xive: hardwire the Physical CAM line of the thread context
By default on P9, the HW CAM line (23bits) is hardwired to : 0x000||0b1||4Bit chip number||7Bit Thread number. When the block group mode is enabled at the controller level (PowerNV), the CAM line is changed for CAM compares to : 4Bit chip number||0x001||7Bit Thread number This will require changes in xive_presenter_tctx_match() possibly. This is a lowlevel functionality of the HW controller and it is not strictly needed. Leave it for later. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1112,6 +1112,30 @@ XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
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return xrc->get_tctx(xrtr, cs);
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}
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/*
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* By default on P9, the HW CAM line (23bits) is hardwired to :
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*
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* 0x000||0b1||4Bit chip number||7Bit Thread number.
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*
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* When the block grouping is enabled, the CAM line is changed to :
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*
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* 4Bit chip number||0x001||7Bit Thread number.
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*/
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static uint32_t hw_cam_line(uint8_t chip_id, uint8_t tid)
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{
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return 1 << 11 | (chip_id & 0xf) << 7 | (tid & 0x7f);
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}
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static bool xive_presenter_tctx_match_hw(XiveTCTX *tctx,
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uint8_t nvt_blk, uint32_t nvt_idx)
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{
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CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
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uint32_t pir = env->spr_cb[SPR_PIR].default_value;
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return hw_cam_line((pir >> 8) & 0xf, pir & 0x7f) ==
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hw_cam_line(nvt_blk, nvt_idx);
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}
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/*
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* The thread context register words are in big-endian format.
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*/
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@ -1120,6 +1144,7 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
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bool cam_ignore, uint32_t logic_serv)
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{
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uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx);
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uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
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uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
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uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
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uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
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@ -1142,7 +1167,11 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
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/* F=0 & i=0: Specific NVT notification */
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/* TODO (PowerNV) : PHYS ring */
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/* PHYS ring */
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if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) &&
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xive_presenter_tctx_match_hw(tctx, nvt_blk, nvt_idx)) {
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return TM_QW3_HV_PHYS;
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}
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/* HV POOL ring */
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if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) &&
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