intel_iommu: set IR bit for ECAP register
Enable IR in IOMMU Extended Capability register. Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -1956,6 +1956,8 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
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*/
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*/
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static void vtd_init(IntelIOMMUState *s)
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static void vtd_init(IntelIOMMUState *s)
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{
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{
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X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
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memset(s->csr, 0, DMAR_REG_SIZE);
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memset(s->csr, 0, DMAR_REG_SIZE);
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memset(s->wmask, 0, DMAR_REG_SIZE);
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memset(s->wmask, 0, DMAR_REG_SIZE);
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memset(s->w1cmask, 0, DMAR_REG_SIZE);
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memset(s->w1cmask, 0, DMAR_REG_SIZE);
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@ -1977,6 +1979,10 @@ static void vtd_init(IntelIOMMUState *s)
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VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS;
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VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS;
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s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
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s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
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if (x86_iommu->intr_supported) {
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s->ecap |= VTD_ECAP_IR;
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}
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vtd_reset_context_cache(s);
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vtd_reset_context_cache(s);
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vtd_reset_iotlb(s);
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vtd_reset_iotlb(s);
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@ -176,6 +176,8 @@
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/* (offset >> 4) << 8 */
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/* (offset >> 4) << 8 */
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#define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4)
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#define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4)
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#define VTD_ECAP_QI (1ULL << 1)
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#define VTD_ECAP_QI (1ULL << 1)
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/* Interrupt Remapping support */
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#define VTD_ECAP_IR (1ULL << 3)
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/* CAP_REG */
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/* CAP_REG */
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/* (offset >> 4) << 24 */
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/* (offset >> 4) << 24 */
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