target/arm: Honour M-profile FP enable bits
Like AArch64, M-profile floating point has no FPEXC enable bit to gate floating point; so always set the VFPEN TB flag. M-profile also has CPACR and NSACR similar to A-profile; they behave slightly differently: * the CPACR is banked between Secure and Non-Secure * if the NSACR forces a trap then this is taken to the Secure state, not the Non-Secure state Honour the CPACR and NSACR settings. The NSACR handling requires us to borrow the exception.target_el field (usually meaningless for M profile) to distinguish the NOCP UsageFault taken to Secure state from the more usual fault taken to the current security state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190416125744.27770-6-peter.maydell@linaro.org
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@ -7556,6 +7556,25 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
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return target_el;
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}
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/*
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* Return true if the v7M CPACR permits access to the FPU for the specified
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* security state and privilege level.
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*/
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static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv)
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{
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switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
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case 0:
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case 2: /* UNPREDICTABLE: we treat like 0 */
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return false;
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case 1:
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return is_priv;
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case 3:
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return true;
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default:
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g_assert_not_reached();
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}
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}
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static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
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ARMMMUIdx mmu_idx, bool ignfault)
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{
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@ -8815,9 +8834,23 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
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env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;
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break;
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case EXCP_NOCP:
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armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
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env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;
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{
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/*
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* NOCP might be directed to something other than the current
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* security state if this fault is because of NSACR; we indicate
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* the target security state using exception.target_el.
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*/
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int target_secstate;
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if (env->exception.target_el == 3) {
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target_secstate = M_REG_S;
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} else {
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target_secstate = env->v7m.secure;
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}
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armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, target_secstate);
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env->v7m.cfsr[target_secstate] |= R_V7M_CFSR_NOCP_MASK;
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break;
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}
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case EXCP_INVSTATE:
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armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
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env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;
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@ -12751,6 +12784,22 @@ int fp_exception_el(CPUARMState *env, int cur_el)
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return 0;
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}
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if (arm_feature(env, ARM_FEATURE_M)) {
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/* CPACR can cause a NOCP UsageFault taken to current security state */
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if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) {
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return 1;
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}
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if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) {
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if (!extract32(env->v7m.nsacr, 10, 1)) {
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/* FP insns cause a NOCP UsageFault taken to Secure */
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return 3;
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}
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}
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return 0;
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}
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/* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
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* 0, 2 : trap EL0 and EL1/PL1 accesses
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* 1 : trap only EL0 accesses
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@ -12938,7 +12987,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));
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flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
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if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
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|| arm_el_is_aa64(env, 1)) {
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|| arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
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flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
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}
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flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar);
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@ -3399,8 +3399,14 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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* for attempts to execute invalid vfp/neon encodings with FP disabled.
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*/
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if (s->fp_excp_el) {
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gen_exception_insn(s, 4, EXCP_UDEF,
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syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
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s->fp_excp_el);
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} else {
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gen_exception_insn(s, 4, EXCP_UDEF,
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syn_fp_access_trap(1, 0xe, false),
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s->fp_excp_el);
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}
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return 0;
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}
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