target/ppc: Tidy gen_conditional_store
Leave only the minimal amount of code within the STCX macro, moving the rest of the code into gen_conditional_store. Remove the explicit call to gen_check_align; the matching LDAX will have already checked alignment, and we verify the same address. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -3201,14 +3201,17 @@ ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
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ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
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#endif
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static void gen_conditional_store(DisasContext *ctx, TCGv EA,
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int reg, int memop)
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static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)
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{
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TCGLabel *l1 = gen_new_label();
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TCGLabel *l2 = gen_new_label();
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TCGv t0;
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TCGv t0 = tcg_temp_new();
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int reg = rS(ctx->opcode);
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tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
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gen_set_access_type(ctx, ACCESS_RES);
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gen_addr_reg_index(ctx, t0);
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tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
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tcg_temp_free(t0);
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t0 = tcg_temp_new();
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tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
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@ -3232,19 +3235,10 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA,
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tcg_gen_movi_tl(cpu_reserve, -1);
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}
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#define STCX(name, memop) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv t0; \
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int len = MEMOP_GET_SIZE(memop); \
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gen_set_access_type(ctx, ACCESS_RES); \
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t0 = tcg_temp_local_new(); \
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gen_addr_reg_index(ctx, t0); \
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if (len > 1) { \
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gen_check_align(ctx, t0, (len) - 1); \
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} \
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gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
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tcg_temp_free(t0); \
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#define STCX(name, memop) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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gen_conditional_store(ctx, memop); \
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}
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STCX(stbcx_, DEF_MEMOP(MO_UB))
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