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exec: Pass CPUState to cpu_reset_interrupt()

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Move it to qom/cpu.c to avoid build failures depending on include order
of cpu-qom.h and exec/cpu-all.h.

Change opaques of various ..._irq_handler() functions to the
appropriate CPU type to facilitate using cpu_reset_interrupt().

Fix Coding Style issues while at it (missing braces, indentation).

Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-01-17 22:30:20 +01:00
parent 259186a7d2
commit d8ed887bdc
24 changed files with 105 additions and 66 deletions
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7
exec.c
View file

@ -492,13 +492,6 @@ void cpu_single_step(CPUArchState *env, int enabled)
#endif
}
void cpu_reset_interrupt(CPUArchState *env, int mask)
{
CPUState *cpu = ENV_GET_CPU(env);
cpu->interrupt_request &= ~mask;
}
void cpu_exit(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);

8
hw/alpha_typhoon.c
View file

@ -63,10 +63,11 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req)
/* If there are any non-masked interrupts, tell the cpu. */
if (cpu != NULL) {
CPUAlphaState *env = &cpu->env;
CPUState *cs = CPU(cpu);
if (req) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
}
@ -359,16 +360,17 @@ static void cchip_write(void *opaque, hwaddr addr,
AlphaCPU *cpu = s->cchip.cpu[i];
if (cpu != NULL) {
CPUAlphaState *env = &cpu->env;
CPUState *cs = CPU(cpu);
/* IPI can be either cleared or set by the write. */
if (newval & (1 << (i + 8))) {
cpu_interrupt(env, CPU_INTERRUPT_SMP);
} else {
cpu_reset_interrupt(env, CPU_INTERRUPT_SMP);
cpu_reset_interrupt(cs, CPU_INTERRUPT_SMP);
}
/* ITI can only be cleared by the write. */
if ((newval & (1 << (i + 4))) == 0) {
cpu_reset_interrupt(env, CPU_INTERRUPT_TIMER);
cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER);
}
}
}

4
hw/apic.c
View file

@ -187,7 +187,7 @@ void apic_deliver_pic_intr(DeviceState *d, int level)
reset_bit(s->irr, lvt & 0xff);
/* fall through */
case APIC_DM_EXTINT:
cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
break;
}
}
@ -485,7 +485,7 @@ void apic_sipi(DeviceState *d)
{
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);
cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
if (!s->wait_for_sipi)
return;

15
hw/arm/pic_cpu.c
View file

@ -16,19 +16,22 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
CPUState *cs = CPU(cpu);
switch (irq) {
case ARM_PIC_CPU_IRQ:
if (level)
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
else
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
case ARM_PIC_CPU_FIQ:
if (level)
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_FIQ);
else
cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
}
break;
default:
hw_error("arm_pic_cpu_handler: Bad interrupt line %d\n", irq);

4
hw/arm/pxa2xx_pic.c
View file

@ -62,13 +62,13 @@ static void pxa2xx_pic_update(void *opaque)
if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
} else {
cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
}
if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
}
}

13
hw/cris/pic_cpu.c
View file

@ -30,16 +30,19 @@
static void cris_pic_cpu_handler(void *opaque, int irq, int level)
{
CPUCRISState *env = (CPUCRISState *)opaque;
CRISCPU *cpu = opaque;
CPUCRISState *env = &cpu->env;
CPUState *cs = CPU(cpu);
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
if (level)
if (level) {
cpu_interrupt(env, type);
else
cpu_reset_interrupt(env, type);
} else {
cpu_reset_interrupt(cs, type);
}
}
qemu_irq *cris_pic_init_cpu(CPUCRISState *env)
{
return qemu_allocate_irqs(cris_pic_cpu_handler, env, 2);
return qemu_allocate_irqs(cris_pic_cpu_handler, cris_env_get_cpu(env), 2);
}

8
hw/i386/pc.c
View file

@ -190,10 +190,12 @@ static void pic_irq_request(void *opaque, int irq, int level)
env = env->next_cpu;
}
} else {
if (level)
CPUState *cs = CPU(x86_env_get_cpu(env));
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
else
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
}

8
hw/lm32/lm32_boards.c
View file

@ -41,12 +41,14 @@ typedef struct {
static void cpu_irq_handler(void *opaque, int irq, int level)
{
CPULM32State *env = opaque;
LM32CPU *cpu = opaque;
CPULM32State *env = &cpu->env;
CPUState *cs = CPU(cpu);
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
@ -117,7 +119,7 @@ static void lm32_evr_init(QEMUMachineInitArgs *args)
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
/* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, cpu, 1);
env->pic_state = lm32_pic_init(*cpu_irq);
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(env->pic_state, i);

8
hw/lm32/milkymist.c
View file

@ -46,12 +46,14 @@ typedef struct {
static void cpu_irq_handler(void *opaque, int irq, int level)
{
CPULM32State *env = opaque;
LM32CPU *cpu = opaque;
CPULM32State *env = &cpu->env;
CPUState *cs = CPU(cpu);
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
@ -123,7 +125,7 @@ milkymist_init(QEMUMachineInitArgs *args)
0x00, 0x89, 0x00, 0x1d, 1);
/* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, cpu, 1);
env->pic_state = lm32_pic_init(*cpu_irq);
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(env->pic_state, i);

14
hw/microblaze/pic_cpu.c
View file

@ -29,16 +29,20 @@
static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)
{
CPUMBState *env = (CPUMBState *)opaque;
MicroBlazeCPU *cpu = opaque;
CPUMBState *env = &cpu->env;
CPUState *cs = CPU(cpu);
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
if (level)
if (level) {
cpu_interrupt(env, type);
else
cpu_reset_interrupt(env, type);
} else {
cpu_reset_interrupt(cs, type);
}
}
qemu_irq *microblaze_pic_init_cpu(CPUMBState *env)
{
return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2);
return qemu_allocate_irqs(microblaze_pic_cpu_handler, mb_env_get_cpu(env),
2);
}

8
hw/mips/mips_int.c
View file

@ -26,7 +26,9 @@
static void cpu_mips_irq_request(void *opaque, int irq, int level)
{
CPUMIPSState *env = (CPUMIPSState *)opaque;
MIPSCPU *cpu = opaque;
CPUMIPSState *env = &cpu->env;
CPUState *cs = CPU(cpu);
if (irq < 0 || irq > 7)
return;
@ -40,7 +42,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
if (env->CP0_Cause & CP0Ca_IP_mask) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
@ -49,7 +51,7 @@ void cpu_mips_irq_init_cpu(CPUMIPSState *env)
qemu_irq *qi;
int i;
qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);
qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env), 8);
for (i = 0; i < 8; i++) {
env->irq[i] = qi[i];
}

3
hw/openrisc/pic_cpu.c
View file

@ -25,6 +25,7 @@
static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
{
OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
CPUState *cs = CPU(cpu);
int i;
uint32_t irq_bit = 1 << irq;
@ -42,7 +43,7 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) {
cpu_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
cpu->env.picsr &= ~(1 << i);
}
}

6
hw/ppc/ppc.c
View file

@ -52,6 +52,7 @@ static void cpu_ppc_tb_start (CPUPPCState *env);
void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
unsigned int old_pending = env->pending_interrupts;
@ -60,8 +61,9 @@ void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
cpu_interrupt(env, CPU_INTERRUPT_HARD);
} else {
env->pending_interrupts &= ~(1 << n_IRQ);
if (env->pending_interrupts == 0)
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
if (env->pending_interrupts == 0) {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
if (old_pending != env->pending_interrupts) {

9
hw/sh_intc.c
View file

@ -42,15 +42,16 @@ void sh_intc_toggle_source(struct intc_source *source,
pending_changed = 1;
if (pending_changed) {
CPUState *cpu = CPU(sh_env_get_cpu(first_cpu));
if (source->pending) {
source->parent->pending++;
if (source->parent->pending == 1)
cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
}
else {
} else {
source->parent->pending--;
if (source->parent->pending == 0)
cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
if (source->parent->pending == 0) {
cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
}
}
}

4
hw/sparc/leon3.c
View file

@ -67,6 +67,7 @@ void leon3_irq_ack(void *irq_manager, int intno)
static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
{
CPUSPARCState *env = (CPUSPARCState *)opaque;
CPUState *cs;
assert(env != NULL);
@ -89,9 +90,10 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
}
}
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
cs = CPU(sparc_env_get_cpu(env));
trace_leon3_reset_irq(env->interrupt_index & 15);
env->interrupt_index = 0;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}

5
hw/sparc/sun4m.c
View file

@ -230,6 +230,8 @@ void sun4m_irq_info(Monitor *mon, const QDict *qdict)
void cpu_check_irqs(CPUSPARCState *env)
{
CPUState *cs;
if (env->pil_in && (env->interrupt_index == 0 ||
(env->interrupt_index & ~15) == TT_EXTINT)) {
unsigned int i;
@ -247,9 +249,10 @@ void cpu_check_irqs(CPUSPARCState *env)
}
}
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
cs = CPU(sparc_env_get_cpu(env));
trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
env->interrupt_index = 0;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}

7
hw/sparc64/sun4u.c
View file

@ -276,7 +276,7 @@ void cpu_check_irqs(CPUSPARCState *env)
CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
env->interrupt_index);
env->interrupt_index = 0;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
return;
}
@ -309,7 +309,7 @@ void cpu_check_irqs(CPUSPARCState *env)
"current interrupt %x\n",
pil, env->pil_in, env->softint, env->interrupt_index);
env->interrupt_index = 0;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
@ -344,8 +344,9 @@ static void cpu_set_ivec_irq(void *opaque, int irq, int level)
} else {
if (env->ivec_status & 0x20) {
CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
cs = CPU(cpu);
env->ivec_status &= ~0x20;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
}

9
hw/unicore32/puv3.c
View file

@ -26,13 +26,15 @@
static void puv3_intc_cpu_handler(void *opaque, int irq, int level)
{
CPUUniCore32State *env = opaque;
UniCore32CPU *cpu = opaque;
CPUUniCore32State *env = &cpu->env;
CPUState *cs = CPU(cpu);
assert(irq == 0);
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
@ -44,7 +46,8 @@ static void puv3_soc_init(CPUUniCore32State *env)
int i;
/* Initialize interrupt controller */
cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler, env, 1);
cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler,
uc32_env_get_cpu(env), 1);
dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, *cpu_intc);
for (i = 0; i < PUV3_IRQS_NR; i++) {
irqs[i] = qdev_get_gpio_in(dev, i);

2
hw/xtensa/pic_cpu.c
View file

@ -80,7 +80,7 @@ void check_interrupts(CPUXtensaState *env)
}
}
env->pending_irq_level = 0;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
static void xtensa_set_irq(void *opaque, int irq, int active)

2
include/exec/cpu-all.h
View file

@ -434,8 +434,6 @@ static inline void cpu_interrupt(CPUArchState *s, int mask)
void cpu_interrupt(CPUArchState *env, int mask);
#endif /* USER_ONLY */
void cpu_reset_interrupt(CPUArchState *env, int mask);
void cpu_exit(CPUArchState *s);
/* Breakpoint/watchpoint flags */

9
include/qom/cpu.h
View file

@ -221,5 +221,14 @@ void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
*/
CPUState *qemu_get_cpu(int index);
/**
* cpu_reset_interrupt:
* @cpu: The CPU to clear the interrupt on.
* @mask: The interrupt mask to clear.
*
* Resets interrupts on the vCPU @cpu.
*/
void cpu_reset_interrupt(CPUState *cpu, int mask);
#endif

5
qom/cpu.c
View file

@ -21,6 +21,11 @@
#include "qom/cpu.h"
#include "qemu-common.h"
void cpu_reset_interrupt(CPUState *cpu, int mask)
{
cpu->interrupt_request &= ~mask;
}
void cpu_reset(CPUState *cpu)
{
CPUClass *klass = CPU_GET_CLASS(cpu);

8
target-m68k/helper.c
View file

@ -312,14 +312,16 @@ int cpu_m68k_handle_mmu_fault (CPUM68KState *env, target_ulong address, int rw,
simplicitly we calculate it when the interrupt is signalled. */
void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector)
{
CPUState *cs = CPU(cpu);
CPUM68KState *env = &cpu->env;
env->pending_level = level;
env->pending_vector = vector;
if (level)
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
else
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
#endif

5
target-mips/op_helper.c
View file

@ -534,12 +534,11 @@ static inline void mips_vpe_wake(CPUMIPSState *c)
static inline void mips_vpe_sleep(MIPSCPU *cpu)
{
CPUState *cs = CPU(cpu);
CPUMIPSState *c = &cpu->env;
/* The VPE was shut off, really go to bed.
Reset any old _WAKE requests. */
cs->halted = 1;
cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
}
static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
@ -2104,7 +2103,7 @@ void helper_wait(CPUMIPSState *env)
CPUState *cs = CPU(mips_env_get_cpu(env));
cs->halted = 1;
cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE);
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
helper_raise_exception(env, EXCP_HLT);
}