exec: split out non-softmmu-specific parts
Over the years, most parts of exec.c that were not specific to softmmu have been moved to accel/tcg; what's left is mostly the low-level part of the memory API, which includes RAMBlock and AddressSpaceDispatch. However exec.c also hosts 4-500 lines of code for the target specific parts of the CPU QOM object, plus a few functions for user-mode emulation that do not have a better place (they are not TCG-specific so accel/tcg/user-exec.c is not a good place either). Move these parts to a new file, so that exec.c can be moved to softmmu/physmem.c. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>stable-6.0
Paolo Bonzini
parent
800d4deda0
commit
d9f24bf572
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@ -117,7 +117,6 @@ R: Paolo Bonzini <pbonzini@redhat.com>
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S: Maintained
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F: softmmu/cpus.c
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F: cpus-common.c
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F: exec.c
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F: accel/tcg/
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F: accel/stubs/tcg-stub.c
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F: scripts/decodetree.py
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@ -1525,6 +1524,7 @@ Machine core
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M: Eduardo Habkost <ehabkost@redhat.com>
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M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
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S: Supported
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F: cpu.c
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F: hw/core/cpu.c
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F: hw/core/machine-qmp-cmds.c
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F: hw/core/machine.c
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@ -2284,8 +2284,8 @@ F: include/exec/ramblock.h
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F: softmmu/dma-helpers.c
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F: softmmu/ioport.c
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F: softmmu/memory.c
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F: softmmu/physmem.c
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F: include/exec/memory-internal.h
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F: exec.c
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F: scripts/coccinelle/memory-region-housekeeping.cocci
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SPICE
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@ -0,0 +1,452 @@
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/*
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* Target-specific parts of the CPU object
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qapi/error.h"
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#include "exec/target_page.h"
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#include "hw/qdev-core.h"
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#include "hw/qdev-properties.h"
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#include "qemu/error-report.h"
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#include "migration/vmstate.h"
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#ifdef CONFIG_USER_ONLY
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#include "qemu.h"
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#else
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#include "exec/address-spaces.h"
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#endif
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#include "sysemu/tcg.h"
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#include "sysemu/kvm.h"
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#include "sysemu/replay.h"
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#include "translate-all.h"
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#include "exec/log.h"
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uintptr_t qemu_host_page_size;
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intptr_t qemu_host_page_mask;
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#ifndef CONFIG_USER_ONLY
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static int cpu_common_post_load(void *opaque, int version_id)
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{
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CPUState *cpu = opaque;
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/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
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version_id is increased. */
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cpu->interrupt_request &= ~0x01;
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tlb_flush(cpu);
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/* loadvm has just updated the content of RAM, bypassing the
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* usual mechanisms that ensure we flush TBs for writes to
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* memory we've translated code from. So we must flush all TBs,
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* which will now be stale.
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*/
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tb_flush(cpu);
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return 0;
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}
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static int cpu_common_pre_load(void *opaque)
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{
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CPUState *cpu = opaque;
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cpu->exception_index = -1;
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return 0;
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}
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static bool cpu_common_exception_index_needed(void *opaque)
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{
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CPUState *cpu = opaque;
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return tcg_enabled() && cpu->exception_index != -1;
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}
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static const VMStateDescription vmstate_cpu_common_exception_index = {
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.name = "cpu_common/exception_index",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = cpu_common_exception_index_needed,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(exception_index, CPUState),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool cpu_common_crash_occurred_needed(void *opaque)
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{
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CPUState *cpu = opaque;
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return cpu->crash_occurred;
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}
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static const VMStateDescription vmstate_cpu_common_crash_occurred = {
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.name = "cpu_common/crash_occurred",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = cpu_common_crash_occurred_needed,
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.fields = (VMStateField[]) {
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VMSTATE_BOOL(crash_occurred, CPUState),
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VMSTATE_END_OF_LIST()
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}
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};
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const VMStateDescription vmstate_cpu_common = {
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.name = "cpu_common",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_load = cpu_common_pre_load,
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.post_load = cpu_common_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(halted, CPUState),
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VMSTATE_UINT32(interrupt_request, CPUState),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_cpu_common_exception_index,
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&vmstate_cpu_common_crash_occurred,
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NULL
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}
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};
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#endif
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void cpu_exec_unrealizefn(CPUState *cpu)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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tlb_destroy(cpu);
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cpu_list_remove(cpu);
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#ifdef CONFIG_USER_ONLY
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assert(cc->vmsd == NULL);
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#else
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if (cc->vmsd != NULL) {
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vmstate_unregister(NULL, cc->vmsd, cpu);
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}
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if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
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vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
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}
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tcg_iommu_free_notifier_list(cpu);
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#endif
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}
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Property cpu_common_props[] = {
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#ifndef CONFIG_USER_ONLY
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/* Create a memory property for softmmu CPU object,
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* so users can wire up its memory. (This can't go in hw/core/cpu.c
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* because that file is compiled only once for both user-mode
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* and system builds.) The default if no link is set up is to use
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* the system address space.
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*/
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DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
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MemoryRegion *),
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#endif
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DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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void cpu_exec_initfn(CPUState *cpu)
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{
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cpu->as = NULL;
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cpu->num_ases = 0;
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#ifndef CONFIG_USER_ONLY
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cpu->thread_id = qemu_get_thread_id();
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cpu->memory = get_system_memory();
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object_ref(OBJECT(cpu->memory));
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#endif
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}
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void cpu_exec_realizefn(CPUState *cpu, Error **errp)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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static bool tcg_target_initialized;
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cpu_list_add(cpu);
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if (tcg_enabled() && !tcg_target_initialized) {
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tcg_target_initialized = true;
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cc->tcg_initialize();
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}
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tlb_init(cpu);
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qemu_plugin_vcpu_init_hook(cpu);
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#ifdef CONFIG_USER_ONLY
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assert(cc->vmsd == NULL);
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#else /* !CONFIG_USER_ONLY */
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if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
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vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
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}
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if (cc->vmsd != NULL) {
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vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
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}
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tcg_iommu_init_notifier_list(cpu);
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#endif
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}
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const char *parse_cpu_option(const char *cpu_option)
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{
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ObjectClass *oc;
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CPUClass *cc;
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gchar **model_pieces;
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const char *cpu_type;
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model_pieces = g_strsplit(cpu_option, ",", 2);
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if (!model_pieces[0]) {
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error_report("-cpu option cannot be empty");
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exit(1);
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}
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oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
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if (oc == NULL) {
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error_report("unable to find CPU model '%s'", model_pieces[0]);
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g_strfreev(model_pieces);
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exit(EXIT_FAILURE);
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}
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cpu_type = object_class_get_name(oc);
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cc = CPU_CLASS(oc);
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cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
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g_strfreev(model_pieces);
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return cpu_type;
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}
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#if defined(CONFIG_USER_ONLY)
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void tb_invalidate_phys_addr(target_ulong addr)
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{
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mmap_lock();
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tb_invalidate_phys_page_range(addr, addr + 1);
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mmap_unlock();
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}
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static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
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{
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tb_invalidate_phys_addr(pc);
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}
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#else
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void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
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{
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ram_addr_t ram_addr;
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MemoryRegion *mr;
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hwaddr l = 1;
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if (!tcg_enabled()) {
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return;
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}
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RCU_READ_LOCK_GUARD();
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mr = address_space_translate(as, addr, &addr, &l, false, attrs);
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if (!(memory_region_is_ram(mr)
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|| memory_region_is_romd(mr))) {
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return;
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}
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ram_addr = memory_region_get_ram_addr(mr) + addr;
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tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
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}
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static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
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{
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/*
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* There may not be a virtual to physical translation for the pc
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* right now, but there may exist cached TB for this pc.
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* Flush the whole TB cache to force re-translation of such TBs.
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* This is heavyweight, but we're debugging anyway.
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*/
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tb_flush(cpu);
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}
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#endif
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/* Add a breakpoint. */
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int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
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CPUBreakpoint **breakpoint)
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{
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CPUBreakpoint *bp;
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bp = g_malloc(sizeof(*bp));
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bp->pc = pc;
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bp->flags = flags;
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/* keep all GDB-injected breakpoints in front */
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if (flags & BP_GDB) {
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QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
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} else {
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QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
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}
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breakpoint_invalidate(cpu, pc);
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if (breakpoint) {
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*breakpoint = bp;
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}
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return 0;
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}
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/* Remove a specific breakpoint. */
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int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
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{
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CPUBreakpoint *bp;
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QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
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if (bp->pc == pc && bp->flags == flags) {
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cpu_breakpoint_remove_by_ref(cpu, bp);
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return 0;
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}
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}
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return -ENOENT;
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}
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/* Remove a specific breakpoint by reference. */
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void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
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{
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QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
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breakpoint_invalidate(cpu, breakpoint->pc);
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g_free(breakpoint);
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}
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/* Remove all matching breakpoints. */
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void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
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{
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CPUBreakpoint *bp, *next;
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QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
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if (bp->flags & mask) {
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cpu_breakpoint_remove_by_ref(cpu, bp);
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}
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}
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}
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/* enable or disable single step mode. EXCP_DEBUG is returned by the
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CPU loop after each instruction */
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void cpu_single_step(CPUState *cpu, int enabled)
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{
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if (cpu->singlestep_enabled != enabled) {
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cpu->singlestep_enabled = enabled;
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if (kvm_enabled()) {
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kvm_update_guest_debug(cpu, 0);
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} else {
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/* must flush all the translated code to avoid inconsistencies */
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/* XXX: only flush what is necessary */
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tb_flush(cpu);
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}
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}
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}
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void cpu_abort(CPUState *cpu, const char *fmt, ...)
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{
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va_list ap;
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va_list ap2;
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va_start(ap, fmt);
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va_copy(ap2, ap);
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fprintf(stderr, "qemu: fatal: ");
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vfprintf(stderr, fmt, ap);
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fprintf(stderr, "\n");
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cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
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if (qemu_log_separate()) {
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FILE *logfile = qemu_log_lock();
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qemu_log("qemu: fatal: ");
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qemu_log_vprintf(fmt, ap2);
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qemu_log("\n");
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log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
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qemu_log_flush();
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qemu_log_unlock(logfile);
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qemu_log_close();
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}
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va_end(ap2);
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va_end(ap);
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replay_finish();
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#if defined(CONFIG_USER_ONLY)
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{
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struct sigaction act;
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sigfillset(&act.sa_mask);
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act.sa_handler = SIG_DFL;
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act.sa_flags = 0;
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sigaction(SIGABRT, &act, NULL);
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}
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#endif
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abort();
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}
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/* physical memory access (slow version, mainly for debug) */
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#if defined(CONFIG_USER_ONLY)
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int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
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void *ptr, target_ulong len, bool is_write)
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{
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int flags;
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target_ulong l, page;
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void * p;
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uint8_t *buf = ptr;
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while (len > 0) {
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page = addr & TARGET_PAGE_MASK;
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l = (page + TARGET_PAGE_SIZE) - addr;
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if (l > len)
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l = len;
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flags = page_get_flags(page);
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if (!(flags & PAGE_VALID))
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return -1;
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if (is_write) {
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if (!(flags & PAGE_WRITE))
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return -1;
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/* XXX: this code should not depend on lock_user */
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if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
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return -1;
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memcpy(p, buf, l);
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unlock_user(p, addr, l);
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} else {
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if (!(flags & PAGE_READ))
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return -1;
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/* XXX: this code should not depend on lock_user */
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if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
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return -1;
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memcpy(buf, p, l);
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unlock_user(p, addr, 0);
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}
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len -= l;
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buf += l;
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addr += l;
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}
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return 0;
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}
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#endif
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bool target_words_bigendian(void)
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{
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#if defined(TARGET_WORDS_BIGENDIAN)
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return true;
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#else
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return false;
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#endif
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}
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void page_size_init(void)
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{
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/* NOTE: we can always suppose that qemu_host_page_size >=
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TARGET_PAGE_SIZE */
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if (qemu_host_page_size == 0) {
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qemu_host_page_size = qemu_real_host_page_size;
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}
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if (qemu_host_page_size < TARGET_PAGE_SIZE) {
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qemu_host_page_size = TARGET_PAGE_SIZE;
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}
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qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
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}
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@ -14,6 +14,9 @@ void cpu_list_unlock(void);
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void tcg_flush_softmmu_tlb(CPUState *cs);
|
||||
|
||||
void tcg_iommu_init_notifier_list(CPUState *cpu);
|
||||
void tcg_iommu_free_notifier_list(CPUState *cpu);
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
enum device_endian {
|
||||
|
|
|
|||
|
|
@ -1372,7 +1372,7 @@ common_ss.add(files('cpus-common.c'))
|
|||
subdir('softmmu')
|
||||
|
||||
common_ss.add(capstone)
|
||||
specific_ss.add(files('disas.c', 'exec.c', 'gdbstub.c'), capstone, libpmem, libdaxctl)
|
||||
specific_ss.add(files('cpu.c', 'disas.c', 'gdbstub.c'), capstone)
|
||||
specific_ss.add(files('exec-vary.c'))
|
||||
specific_ss.add(when: 'CONFIG_TCG', if_true: files(
|
||||
'fpu/softfloat.c',
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: [files(
|
|||
'balloon.c',
|
||||
'cpus.c',
|
||||
'cpu-throttle.c',
|
||||
'physmem.c',
|
||||
'ioport.c',
|
||||
'memory.c',
|
||||
'memory_mapping.c',
|
||||
|
|
@ -19,7 +20,7 @@ softmmu_ss.add(files(
|
|||
'bootdevice.c',
|
||||
'dma-helpers.c',
|
||||
'qdev-monitor.c',
|
||||
), sdl)
|
||||
), sdl, libpmem, libdaxctl)
|
||||
|
||||
softmmu_ss.add(when: 'CONFIG_TPM', if_true: files('tpm.c'))
|
||||
softmmu_ss.add(when: 'CONFIG_SECCOMP', if_true: [files('qemu-seccomp.c'), seccomp])
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Virtual page mapping
|
||||
* RAM allocation and memory access
|
||||
*
|
||||
* Copyright (c) 2003 Fabrice Bellard
|
||||
*
|
||||
|
|
@ -28,10 +28,8 @@
|
|||
#include "tcg/tcg.h"
|
||||
#include "hw/qdev-core.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
#include "hw/boards.h"
|
||||
#include "hw/xen/xen.h"
|
||||
#endif
|
||||
#include "sysemu/kvm.h"
|
||||
#include "sysemu/sysemu.h"
|
||||
#include "sysemu/tcg.h"
|
||||
|
|
@ -40,9 +38,6 @@
|
|||
#include "qemu/config-file.h"
|
||||
#include "qemu/error-report.h"
|
||||
#include "qemu/qemu-print.h"
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
#include "qemu.h"
|
||||
#else /* !CONFIG_USER_ONLY */
|
||||
#include "exec/memory.h"
|
||||
#include "exec/ioport.h"
|
||||
#include "sysemu/dma.h"
|
||||
|
|
@ -56,7 +51,6 @@
|
|||
#include <linux/falloc.h>
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#include "qemu/rcu_queue.h"
|
||||
#include "qemu/main-loop.h"
|
||||
#include "translate-all.h"
|
||||
|
|
@ -83,7 +77,6 @@
|
|||
|
||||
//#define DEBUG_SUBPAGE
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
/* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
|
||||
* are protected by the ramlist lock.
|
||||
*/
|
||||
|
|
@ -96,12 +89,6 @@ AddressSpace address_space_io;
|
|||
AddressSpace address_space_memory;
|
||||
|
||||
static MemoryRegion io_mem_unassigned;
|
||||
#endif
|
||||
|
||||
uintptr_t qemu_host_page_size;
|
||||
intptr_t qemu_host_page_mask;
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
typedef struct PhysPageEntry PhysPageEntry;
|
||||
|
||||
|
|
@ -179,10 +166,6 @@ struct DirtyBitmapSnapshot {
|
|||
unsigned long dirty[];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
|
||||
{
|
||||
static unsigned alloc_hint = 16;
|
||||
|
|
@ -661,7 +644,7 @@ static void tcg_register_iommu_notifier(CPUState *cpu,
|
|||
}
|
||||
}
|
||||
|
||||
static void tcg_iommu_free_notifier_list(CPUState *cpu)
|
||||
void tcg_iommu_free_notifier_list(CPUState *cpu)
|
||||
{
|
||||
/* Destroy the CPU's notifier list */
|
||||
int i;
|
||||
|
|
@ -675,6 +658,11 @@ static void tcg_iommu_free_notifier_list(CPUState *cpu)
|
|||
g_array_free(cpu->iommu_notifiers, true);
|
||||
}
|
||||
|
||||
void tcg_iommu_init_notifier_list(CPUState *cpu)
|
||||
{
|
||||
cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *));
|
||||
}
|
||||
|
||||
/* Called from RCU critical section */
|
||||
MemoryRegionSection *
|
||||
address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
|
||||
|
|
@ -732,91 +720,6 @@ address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
|
|||
translate_fail:
|
||||
return &d->map.sections[PHYS_SECTION_UNASSIGNED];
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
static int cpu_common_post_load(void *opaque, int version_id)
|
||||
{
|
||||
CPUState *cpu = opaque;
|
||||
|
||||
/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
|
||||
version_id is increased. */
|
||||
cpu->interrupt_request &= ~0x01;
|
||||
tlb_flush(cpu);
|
||||
|
||||
/* loadvm has just updated the content of RAM, bypassing the
|
||||
* usual mechanisms that ensure we flush TBs for writes to
|
||||
* memory we've translated code from. So we must flush all TBs,
|
||||
* which will now be stale.
|
||||
*/
|
||||
tb_flush(cpu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpu_common_pre_load(void *opaque)
|
||||
{
|
||||
CPUState *cpu = opaque;
|
||||
|
||||
cpu->exception_index = -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool cpu_common_exception_index_needed(void *opaque)
|
||||
{
|
||||
CPUState *cpu = opaque;
|
||||
|
||||
return tcg_enabled() && cpu->exception_index != -1;
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_cpu_common_exception_index = {
|
||||
.name = "cpu_common/exception_index",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.needed = cpu_common_exception_index_needed,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_INT32(exception_index, CPUState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static bool cpu_common_crash_occurred_needed(void *opaque)
|
||||
{
|
||||
CPUState *cpu = opaque;
|
||||
|
||||
return cpu->crash_occurred;
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_cpu_common_crash_occurred = {
|
||||
.name = "cpu_common/crash_occurred",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.needed = cpu_common_crash_occurred_needed,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_BOOL(crash_occurred, CPUState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
const VMStateDescription vmstate_cpu_common = {
|
||||
.name = "cpu_common",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.pre_load = cpu_common_pre_load,
|
||||
.post_load = cpu_common_post_load,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32(halted, CPUState),
|
||||
VMSTATE_UINT32(interrupt_request, CPUState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
},
|
||||
.subsections = (const VMStateDescription*[]) {
|
||||
&vmstate_cpu_common_exception_index,
|
||||
&vmstate_cpu_common_crash_occurred,
|
||||
NULL
|
||||
}
|
||||
};
|
||||
|
||||
void cpu_address_space_init(CPUState *cpu, int asidx,
|
||||
const char *prefix, MemoryRegion *mr)
|
||||
|
|
@ -860,155 +763,7 @@ AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
|
|||
/* Return the AddressSpace corresponding to the specified index */
|
||||
return cpu->cpu_ases[asidx].as;
|
||||
}
|
||||
#endif
|
||||
|
||||
void cpu_exec_unrealizefn(CPUState *cpu)
|
||||
{
|
||||
CPUClass *cc = CPU_GET_CLASS(cpu);
|
||||
|
||||
tlb_destroy(cpu);
|
||||
cpu_list_remove(cpu);
|
||||
|
||||
if (cc->vmsd != NULL) {
|
||||
vmstate_unregister(NULL, cc->vmsd, cpu);
|
||||
}
|
||||
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
|
||||
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
|
||||
}
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
tcg_iommu_free_notifier_list(cpu);
|
||||
#endif
|
||||
}
|
||||
|
||||
Property cpu_common_props[] = {
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
/* Create a memory property for softmmu CPU object,
|
||||
* so users can wire up its memory. (This can't go in hw/core/cpu.c
|
||||
* because that file is compiled only once for both user-mode
|
||||
* and system builds.) The default if no link is set up is to use
|
||||
* the system address space.
|
||||
*/
|
||||
DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
|
||||
MemoryRegion *),
|
||||
#endif
|
||||
DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
void cpu_exec_initfn(CPUState *cpu)
|
||||
{
|
||||
cpu->as = NULL;
|
||||
cpu->num_ases = 0;
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
cpu->thread_id = qemu_get_thread_id();
|
||||
cpu->memory = system_memory;
|
||||
object_ref(OBJECT(cpu->memory));
|
||||
#endif
|
||||
}
|
||||
|
||||
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
|
||||
{
|
||||
CPUClass *cc = CPU_GET_CLASS(cpu);
|
||||
static bool tcg_target_initialized;
|
||||
|
||||
cpu_list_add(cpu);
|
||||
|
||||
if (tcg_enabled() && !tcg_target_initialized) {
|
||||
tcg_target_initialized = true;
|
||||
cc->tcg_initialize();
|
||||
}
|
||||
tlb_init(cpu);
|
||||
|
||||
qemu_plugin_vcpu_init_hook(cpu);
|
||||
|
||||
#ifdef CONFIG_USER_ONLY
|
||||
assert(cc->vmsd == NULL);
|
||||
#else /* !CONFIG_USER_ONLY */
|
||||
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
|
||||
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
|
||||
}
|
||||
if (cc->vmsd != NULL) {
|
||||
vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
|
||||
}
|
||||
|
||||
cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *));
|
||||
#endif
|
||||
}
|
||||
|
||||
const char *parse_cpu_option(const char *cpu_option)
|
||||
{
|
||||
ObjectClass *oc;
|
||||
CPUClass *cc;
|
||||
gchar **model_pieces;
|
||||
const char *cpu_type;
|
||||
|
||||
model_pieces = g_strsplit(cpu_option, ",", 2);
|
||||
if (!model_pieces[0]) {
|
||||
error_report("-cpu option cannot be empty");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
|
||||
if (oc == NULL) {
|
||||
error_report("unable to find CPU model '%s'", model_pieces[0]);
|
||||
g_strfreev(model_pieces);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
cpu_type = object_class_get_name(oc);
|
||||
cc = CPU_CLASS(oc);
|
||||
cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
|
||||
g_strfreev(model_pieces);
|
||||
return cpu_type;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
void tb_invalidate_phys_addr(target_ulong addr)
|
||||
{
|
||||
mmap_lock();
|
||||
tb_invalidate_phys_page_range(addr, addr + 1);
|
||||
mmap_unlock();
|
||||
}
|
||||
|
||||
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
|
||||
{
|
||||
tb_invalidate_phys_addr(pc);
|
||||
}
|
||||
#else
|
||||
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
|
||||
{
|
||||
ram_addr_t ram_addr;
|
||||
MemoryRegion *mr;
|
||||
hwaddr l = 1;
|
||||
|
||||
if (!tcg_enabled()) {
|
||||
return;
|
||||
}
|
||||
|
||||
RCU_READ_LOCK_GUARD();
|
||||
mr = address_space_translate(as, addr, &addr, &l, false, attrs);
|
||||
if (!(memory_region_is_ram(mr)
|
||||
|| memory_region_is_romd(mr))) {
|
||||
return;
|
||||
}
|
||||
ram_addr = memory_region_get_ram_addr(mr) + addr;
|
||||
tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
|
||||
}
|
||||
|
||||
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
|
||||
{
|
||||
/*
|
||||
* There may not be a virtual to physical translation for the pc
|
||||
* right now, but there may exist cached TB for this pc.
|
||||
* Flush the whole TB cache to force re-translation of such TBs.
|
||||
* This is heavyweight, but we're debugging anyway.
|
||||
*/
|
||||
tb_flush(cpu);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
/* Add a watchpoint. */
|
||||
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
|
||||
int flags, CPUWatchpoint **watchpoint)
|
||||
|
|
@ -1117,123 +872,7 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
|
|||
}
|
||||
return ret;
|
||||
}
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
/* Add a breakpoint. */
|
||||
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
|
||||
CPUBreakpoint **breakpoint)
|
||||
{
|
||||
CPUBreakpoint *bp;
|
||||
|
||||
bp = g_malloc(sizeof(*bp));
|
||||
|
||||
bp->pc = pc;
|
||||
bp->flags = flags;
|
||||
|
||||
/* keep all GDB-injected breakpoints in front */
|
||||
if (flags & BP_GDB) {
|
||||
QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
|
||||
} else {
|
||||
QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
|
||||
}
|
||||
|
||||
breakpoint_invalidate(cpu, pc);
|
||||
|
||||
if (breakpoint) {
|
||||
*breakpoint = bp;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Remove a specific breakpoint. */
|
||||
int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
|
||||
{
|
||||
CPUBreakpoint *bp;
|
||||
|
||||
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
|
||||
if (bp->pc == pc && bp->flags == flags) {
|
||||
cpu_breakpoint_remove_by_ref(cpu, bp);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
/* Remove a specific breakpoint by reference. */
|
||||
void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
|
||||
{
|
||||
QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
|
||||
|
||||
breakpoint_invalidate(cpu, breakpoint->pc);
|
||||
|
||||
g_free(breakpoint);
|
||||
}
|
||||
|
||||
/* Remove all matching breakpoints. */
|
||||
void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
|
||||
{
|
||||
CPUBreakpoint *bp, *next;
|
||||
|
||||
QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
|
||||
if (bp->flags & mask) {
|
||||
cpu_breakpoint_remove_by_ref(cpu, bp);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* enable or disable single step mode. EXCP_DEBUG is returned by the
|
||||
CPU loop after each instruction */
|
||||
void cpu_single_step(CPUState *cpu, int enabled)
|
||||
{
|
||||
if (cpu->singlestep_enabled != enabled) {
|
||||
cpu->singlestep_enabled = enabled;
|
||||
if (kvm_enabled()) {
|
||||
kvm_update_guest_debug(cpu, 0);
|
||||
} else {
|
||||
/* must flush all the translated code to avoid inconsistencies */
|
||||
/* XXX: only flush what is necessary */
|
||||
tb_flush(cpu);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void cpu_abort(CPUState *cpu, const char *fmt, ...)
|
||||
{
|
||||
va_list ap;
|
||||
va_list ap2;
|
||||
|
||||
va_start(ap, fmt);
|
||||
va_copy(ap2, ap);
|
||||
fprintf(stderr, "qemu: fatal: ");
|
||||
vfprintf(stderr, fmt, ap);
|
||||
fprintf(stderr, "\n");
|
||||
cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
|
||||
if (qemu_log_separate()) {
|
||||
FILE *logfile = qemu_log_lock();
|
||||
qemu_log("qemu: fatal: ");
|
||||
qemu_log_vprintf(fmt, ap2);
|
||||
qemu_log("\n");
|
||||
log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
|
||||
qemu_log_flush();
|
||||
qemu_log_unlock(logfile);
|
||||
qemu_log_close();
|
||||
}
|
||||
va_end(ap2);
|
||||
va_end(ap);
|
||||
replay_finish();
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
{
|
||||
struct sigaction act;
|
||||
sigfillset(&act.sa_mask);
|
||||
act.sa_handler = SIG_DFL;
|
||||
act.sa_flags = 0;
|
||||
sigaction(SIGABRT, &act, NULL);
|
||||
}
|
||||
#endif
|
||||
abort();
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
/* Called from RCU critical section */
|
||||
static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
|
||||
{
|
||||
|
|
@ -1420,9 +1059,6 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu,
|
|||
AddressSpaceDispatch *d = flatview_to_dispatch(section->fv);
|
||||
return section - d->map.sections;
|
||||
}
|
||||
#endif /* defined(CONFIG_USER_ONLY) */
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end,
|
||||
uint16_t section);
|
||||
|
|
@ -3023,52 +2659,6 @@ MemoryRegion *get_system_io(void)
|
|||
return system_io;
|
||||
}
|
||||
|
||||
#endif /* !defined(CONFIG_USER_ONLY) */
|
||||
|
||||
/* physical memory access (slow version, mainly for debug) */
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
|
||||
void *ptr, target_ulong len, bool is_write)
|
||||
{
|
||||
int flags;
|
||||
target_ulong l, page;
|
||||
void * p;
|
||||
uint8_t *buf = ptr;
|
||||
|
||||
while (len > 0) {
|
||||
page = addr & TARGET_PAGE_MASK;
|
||||
l = (page + TARGET_PAGE_SIZE) - addr;
|
||||
if (l > len)
|
||||
l = len;
|
||||
flags = page_get_flags(page);
|
||||
if (!(flags & PAGE_VALID))
|
||||
return -1;
|
||||
if (is_write) {
|
||||
if (!(flags & PAGE_WRITE))
|
||||
return -1;
|
||||
/* XXX: this code should not depend on lock_user */
|
||||
if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
|
||||
return -1;
|
||||
memcpy(p, buf, l);
|
||||
unlock_user(p, addr, l);
|
||||
} else {
|
||||
if (!(flags & PAGE_READ))
|
||||
return -1;
|
||||
/* XXX: this code should not depend on lock_user */
|
||||
if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
|
||||
return -1;
|
||||
memcpy(buf, p, l);
|
||||
unlock_user(p, addr, 0);
|
||||
}
|
||||
len -= l;
|
||||
buf += l;
|
||||
addr += l;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
|
||||
hwaddr length)
|
||||
{
|
||||
|
|
@ -3857,18 +3447,7 @@ int qemu_target_page_bits_min(void)
|
|||
{
|
||||
return TARGET_PAGE_BITS_MIN;
|
||||
}
|
||||
#endif
|
||||
|
||||
bool target_words_bigendian(void)
|
||||
{
|
||||
#if defined(TARGET_WORDS_BIGENDIAN)
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
bool cpu_physical_memory_is_io(hwaddr phys_addr)
|
||||
{
|
||||
MemoryRegion*mr;
|
||||
|
|
@ -3998,23 +3577,6 @@ bool ramblock_is_pmem(RAMBlock *rb)
|
|||
return rb->flags & RAM_PMEM;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void page_size_init(void)
|
||||
{
|
||||
/* NOTE: we can always suppose that qemu_host_page_size >=
|
||||
TARGET_PAGE_SIZE */
|
||||
if (qemu_host_page_size == 0) {
|
||||
qemu_host_page_size = qemu_real_host_page_size;
|
||||
}
|
||||
if (qemu_host_page_size < TARGET_PAGE_SIZE) {
|
||||
qemu_host_page_size = TARGET_PAGE_SIZE;
|
||||
}
|
||||
qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
static void mtree_print_phys_entries(int start, int end, int skip, int ptr)
|
||||
{
|
||||
if (start == end - 1) {
|
||||
|
|
@ -4147,5 +3709,3 @@ bool ram_block_discard_is_required(void)
|
|||
{
|
||||
return qatomic_read(&ram_block_discard_disabled) < 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue