target-mips: fix offset calculation for Interrupts
Correct computation of vector offsets for EXCP_EXT_INTERRUPT. For instance, if Cause.IV is 0 the vector offset should be 0x180. Simplify the finding vector number logic for the Vectored Interrupts. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: cosmetic changes] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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@ -565,34 +565,30 @@ void mips_cpu_do_interrupt(CPUState *cs)
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break;
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break;
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case EXCP_EXT_INTERRUPT:
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case EXCP_EXT_INTERRUPT:
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cause = 0;
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cause = 0;
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if (env->CP0_Cause & (1 << CP0Ca_IV))
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if (env->CP0_Cause & (1 << CP0Ca_IV)) {
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offset = 0x200;
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uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
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if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
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if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
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/* Vectored Interrupts. */
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offset = 0x200;
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unsigned int spacing;
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} else {
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unsigned int vector;
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uint32_t vector = 0;
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unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
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uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
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pending &= env->CP0_Status >> 8;
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if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
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/* Compute the Vector Spacing. */
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/* For VEIC mode, the external interrupt controller feeds
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spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
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* the vector through the CP0Cause IP lines. */
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spacing <<= 5;
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vector = pending;
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} else {
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if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
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/* Vectored Interrupts
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/* For VInt mode, the MIPS computes the vector internally. */
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* Mask with Status.IM7-IM0 to get enabled interrupts. */
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for (vector = 7; vector > 0; vector--) {
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pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
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if (pending & (1 << vector)) {
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/* Find the highest-priority interrupt. */
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/* Found it. */
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while (pending >>= 1) {
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break;
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vector++;
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}
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}
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}
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}
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} else {
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offset = 0x200 + (vector * (spacing << 5));
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/* For VEIC mode, the external interrupt controller feeds the
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vector through the CP0Cause IP lines. */
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vector = pending;
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}
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}
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offset = 0x200 + vector * spacing;
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}
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}
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goto set_EPC;
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goto set_EPC;
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case EXCP_LTLBL:
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case EXCP_LTLBL:
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@ -1432,7 +1432,6 @@ void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
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void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
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void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
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{
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{
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/* vectored interrupts not implemented, no performance counters. */
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env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
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env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
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}
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}
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@ -1473,7 +1472,6 @@ target_ulong helper_mftc0_ebase(CPUMIPSState *env)
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void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
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void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
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{
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{
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/* vectored interrupts not implemented */
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env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
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env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
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}
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}
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