target-alpha: Reduce internal processor registers for user-mode.
The existing set of IPRs is totally irrelevant to user-mode emulation. Indeed, they most are irrelevant to implementing kernel-mode emulation, and would only be relevant to PAL-mode emulation, which I suspect that no one will ever attempt. Reducing the set of processor registers reduces the size of the CPU state. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -3054,10 +3054,8 @@ int main(int argc, char **argv, char **envp)
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for(i = 0; i < 28; i++) {
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for(i = 0; i < 28; i++) {
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env->ir[i] = ((abi_ulong *)regs)[i];
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env->ir[i] = ((abi_ulong *)regs)[i];
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}
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}
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env->ipr[IPR_USP] = regs->usp;
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env->ir[IR_SP] = regs->usp;
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env->ir[30] = regs->usp;
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env->pc = regs->pc;
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env->pc = regs->pc;
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env->unique = regs->unique;
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}
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}
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#elif defined(TARGET_CRIS)
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#elif defined(TARGET_CRIS)
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{
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{
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@ -193,6 +193,11 @@ enum {
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/* Internal processor registers */
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/* Internal processor registers */
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/* XXX: TOFIX: most of those registers are implementation dependant */
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/* XXX: TOFIX: most of those registers are implementation dependant */
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enum {
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enum {
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#if defined(CONFIG_USER_ONLY)
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IPR_EXC_ADDR,
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IPR_EXC_SUM,
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IPR_EXC_MASK,
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#else
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/* Ebox IPRs */
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/* Ebox IPRs */
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IPR_CC = 0xC0, /* 21264 */
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IPR_CC = 0xC0, /* 21264 */
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IPR_CC_CTL = 0xC1, /* 21264 */
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IPR_CC_CTL = 0xC1, /* 21264 */
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@ -306,6 +311,7 @@ enum {
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IPR_VPTB,
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IPR_VPTB,
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IPR_WHAMI,
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IPR_WHAMI,
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IPR_ALT_MODE,
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IPR_ALT_MODE,
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#endif
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IPR_LAST,
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IPR_LAST,
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};
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};
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@ -2721,7 +2721,6 @@ static const struct cpu_def_t cpu_defs[] = {
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CPUAlphaState * cpu_alpha_init (const char *cpu_model)
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CPUAlphaState * cpu_alpha_init (const char *cpu_model)
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{
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{
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CPUAlphaState *env;
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CPUAlphaState *env;
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uint64_t hwpcb;
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int implver, amask, i, max;
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int implver, amask, i, max;
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env = qemu_mallocz(sizeof(CPUAlphaState));
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env = qemu_mallocz(sizeof(CPUAlphaState));
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@ -2752,24 +2751,34 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model)
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| FPCR_UNFD | FPCR_INED | FPCR_DNOD));
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| FPCR_UNFD | FPCR_INED | FPCR_DNOD));
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#endif
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#endif
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pal_init(env);
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pal_init(env);
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/* Initialize IPR */
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/* Initialize IPR */
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hwpcb = env->ipr[IPR_PCBB];
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#if defined (CONFIG_USER_ONLY)
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env->ipr[IPR_ASN] = 0;
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env->ipr[IPR_EXC_ADDR] = 0;
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env->ipr[IPR_ASTEN] = 0;
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env->ipr[IPR_EXC_SUM] = 0;
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env->ipr[IPR_ASTSR] = 0;
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env->ipr[IPR_EXC_MASK] = 0;
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env->ipr[IPR_DATFX] = 0;
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#else
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/* XXX: fix this */
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{
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// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
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uint64_t hwpcb;
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// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
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hwpcb = env->ipr[IPR_PCBB];
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// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
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env->ipr[IPR_ASN] = 0;
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// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
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env->ipr[IPR_ASTEN] = 0;
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env->ipr[IPR_FEN] = 0;
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env->ipr[IPR_ASTSR] = 0;
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env->ipr[IPR_IPL] = 31;
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env->ipr[IPR_DATFX] = 0;
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env->ipr[IPR_MCES] = 0;
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/* XXX: fix this */
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env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
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// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
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// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
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// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
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env->ipr[IPR_SISR] = 0;
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// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
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env->ipr[IPR_VIRBND] = -1ULL;
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// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
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env->ipr[IPR_FEN] = 0;
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env->ipr[IPR_IPL] = 31;
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env->ipr[IPR_MCES] = 0;
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env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
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// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
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env->ipr[IPR_SISR] = 0;
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env->ipr[IPR_VIRBND] = -1ULL;
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}
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#endif
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qemu_init_vcpu(env);
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qemu_init_vcpu(env);
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return env;
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return env;
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