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target/riscv: Define ePMP mseccfg

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Use address 0x390 and 0x391 for the ePMP CSRs.

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Hou Weiying 2021-04-19 16:16:38 +10:00 committed by Alistair Francis
parent 94c6ba83c1
commit db9f1dac48
1 changed files with 3 additions and 0 deletions
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3
target/riscv/cpu_bits.h
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@ -220,6 +220,9 @@
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b
/* Enhanced Physical Memory Protection (ePMP) */
#define CSR_MSECCFG 0x390
#define CSR_MSECCFGH 0x391
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1