intel_iommu: support passthrough (PT)
Hardware support for VT-d device passthrough. Although current Linux can live with iommu=pt even without this, but this is faster than when using software passthrough. Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Liu, Yi L <yi.l.liu@linux.intel.com> Reviewed-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
parent
f80c98740e
commit
dbaabb25f4
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@ -613,6 +613,11 @@ static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu,
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return false;
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return false;
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}
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}
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break;
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break;
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case VTD_CONTEXT_TT_PASS_THROUGH:
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if (!x86_iommu->pt_supported) {
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return false;
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}
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break;
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default:
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default:
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/* Unknwon type */
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/* Unknwon type */
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return false;
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return false;
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@ -660,6 +665,29 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
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}
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}
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}
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}
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/* Find the VTD address space associated with a given bus number */
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static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
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{
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VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
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if (!vtd_bus) {
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/*
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* Iterate over the registered buses to find the one which
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* currently hold this bus number, and update the bus_num
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* lookup table:
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*/
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GHashTableIter iter;
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g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
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while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
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if (pci_bus_num(vtd_bus->bus) == bus_num) {
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s->vtd_as_by_bus_num[bus_num] = vtd_bus;
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return vtd_bus;
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}
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}
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}
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return vtd_bus;
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}
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/* Given the @iova, get relevant @slptep. @slpte_level will be the last level
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/* Given the @iova, get relevant @slptep. @slpte_level will be the last level
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* of the translation, can be used for deciding the size of large page.
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* of the translation, can be used for deciding the size of large page.
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*/
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*/
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@ -906,6 +934,91 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
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return 0;
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return 0;
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}
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}
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/*
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* Fetch translation type for specific device. Returns <0 if error
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* happens, otherwise return the shifted type to check against
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* VTD_CONTEXT_TT_*.
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*/
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static int vtd_dev_get_trans_type(VTDAddressSpace *as)
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{
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IntelIOMMUState *s;
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VTDContextEntry ce;
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int ret;
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s = as->iommu_state;
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ret = vtd_dev_to_context_entry(s, pci_bus_num(as->bus),
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as->devfn, &ce);
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if (ret) {
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return ret;
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}
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return vtd_ce_get_type(&ce);
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}
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static bool vtd_dev_pt_enabled(VTDAddressSpace *as)
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{
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int ret;
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assert(as);
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ret = vtd_dev_get_trans_type(as);
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if (ret < 0) {
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/*
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* Possibly failed to parse the context entry for some reason
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* (e.g., during init, or any guest configuration errors on
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* context entries). We should assume PT not enabled for
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* safety.
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*/
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return false;
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}
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return ret == VTD_CONTEXT_TT_PASS_THROUGH;
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}
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/* Return whether the device is using IOMMU translation. */
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static bool vtd_switch_address_space(VTDAddressSpace *as)
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{
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bool use_iommu;
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assert(as);
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use_iommu = as->iommu_state->dmar_enabled & !vtd_dev_pt_enabled(as);
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trace_vtd_switch_address_space(pci_bus_num(as->bus),
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VTD_PCI_SLOT(as->devfn),
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VTD_PCI_FUNC(as->devfn),
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use_iommu);
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/* Turn off first then on the other */
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if (use_iommu) {
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memory_region_set_enabled(&as->sys_alias, false);
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memory_region_set_enabled(&as->iommu, true);
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} else {
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memory_region_set_enabled(&as->iommu, false);
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memory_region_set_enabled(&as->sys_alias, true);
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}
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return use_iommu;
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}
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static void vtd_switch_address_space_all(IntelIOMMUState *s)
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{
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GHashTableIter iter;
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VTDBus *vtd_bus;
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int i;
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g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
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while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
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for (i = 0; i < X86_IOMMU_PCI_DEVFN_MAX; i++) {
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if (!vtd_bus->dev_as[i]) {
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continue;
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}
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vtd_switch_address_space(vtd_bus->dev_as[i]);
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}
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}
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}
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static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
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static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
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{
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{
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return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
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return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
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@ -943,6 +1056,31 @@ static inline bool vtd_is_interrupt_addr(hwaddr addr)
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return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
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return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
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}
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}
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static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id)
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{
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VTDBus *vtd_bus;
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VTDAddressSpace *vtd_as;
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bool success = false;
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vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
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if (!vtd_bus) {
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goto out;
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}
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vtd_as = vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)];
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if (!vtd_as) {
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goto out;
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}
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if (vtd_switch_address_space(vtd_as) == false) {
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/* We switched off IOMMU region successfully. */
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success = true;
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}
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out:
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trace_vtd_pt_enable_fast_path(source_id, success);
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}
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/* Map dev to context-entry then do a paging-structures walk to do a iommu
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/* Map dev to context-entry then do a paging-structures walk to do a iommu
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* translation.
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* translation.
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*
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*
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@ -1014,6 +1152,30 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
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cc_entry->context_cache_gen = s->context_cache_gen;
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cc_entry->context_cache_gen = s->context_cache_gen;
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}
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}
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/*
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* We don't need to translate for pass-through context entries.
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* Also, let's ignore IOTLB caching as well for PT devices.
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*/
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if (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH) {
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entry->translated_addr = entry->iova;
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entry->addr_mask = VTD_PAGE_SIZE - 1;
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entry->perm = IOMMU_RW;
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trace_vtd_translate_pt(source_id, entry->iova);
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/*
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* When this happens, it means firstly caching-mode is not
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* enabled, and this is the first passthrough translation for
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* the device. Let's enable the fast path for passthrough.
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*
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* When passthrough is disabled again for the device, we can
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* capture it via the context entry invalidation, then the
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* IOMMU region can be swapped back.
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*/
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vtd_pt_enable_fast_path(s, source_id);
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return;
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}
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ret_fr = vtd_iova_to_slpte(&ce, addr, is_write, &slpte, &level,
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ret_fr = vtd_iova_to_slpte(&ce, addr, is_write, &slpte, &level,
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&reads, &writes);
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&reads, &writes);
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if (ret_fr) {
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if (ret_fr) {
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@ -1083,6 +1245,7 @@ static void vtd_context_global_invalidate(IntelIOMMUState *s)
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if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
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if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
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vtd_reset_context_cache(s);
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vtd_reset_context_cache(s);
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}
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}
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vtd_switch_address_space_all(s);
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/*
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/*
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* From VT-d spec 6.5.2.1, a global context entry invalidation
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* From VT-d spec 6.5.2.1, a global context entry invalidation
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* should be followed by a IOTLB global invalidation, so we should
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* should be followed by a IOTLB global invalidation, so we should
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@ -1093,29 +1256,6 @@ static void vtd_context_global_invalidate(IntelIOMMUState *s)
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vtd_iommu_replay_all(s);
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vtd_iommu_replay_all(s);
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}
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}
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/* Find the VTD address space currently associated with a given bus number,
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*/
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static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
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{
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VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
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if (!vtd_bus) {
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/* Iterate over the registered buses to find the one
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* which currently hold this bus number, and update the bus_num lookup table:
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*/
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GHashTableIter iter;
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g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
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while (g_hash_table_iter_next (&iter, NULL, (void**)&vtd_bus)) {
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if (pci_bus_num(vtd_bus->bus) == bus_num) {
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s->vtd_as_by_bus_num[bus_num] = vtd_bus;
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return vtd_bus;
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}
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}
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}
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return vtd_bus;
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}
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/* Do a context-cache device-selective invalidation.
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/* Do a context-cache device-selective invalidation.
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* @func_mask: FM field after shifting
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* @func_mask: FM field after shifting
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*/
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*/
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@ -1157,6 +1297,11 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
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trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it),
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trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it),
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VTD_PCI_FUNC(devfn_it));
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VTD_PCI_FUNC(devfn_it));
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vtd_as->context_cache_entry.context_cache_gen = 0;
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vtd_as->context_cache_entry.context_cache_gen = 0;
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/*
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* Do switch address space when needed, in case if the
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* device passthrough bit is switched.
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*/
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vtd_switch_address_space(vtd_as);
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/*
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/*
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* So a device is moving out of (or moving into) a
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* So a device is moving out of (or moving into) a
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* domain, a replay() suites here to notify all the
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* domain, a replay() suites here to notify all the
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@ -1389,42 +1534,6 @@ static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s)
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vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS);
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vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS);
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}
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}
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static void vtd_switch_address_space(VTDAddressSpace *as)
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{
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assert(as);
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trace_vtd_switch_address_space(pci_bus_num(as->bus),
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VTD_PCI_SLOT(as->devfn),
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VTD_PCI_FUNC(as->devfn),
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as->iommu_state->dmar_enabled);
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/* Turn off first then on the other */
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if (as->iommu_state->dmar_enabled) {
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memory_region_set_enabled(&as->sys_alias, false);
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memory_region_set_enabled(&as->iommu, true);
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} else {
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memory_region_set_enabled(&as->iommu, false);
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memory_region_set_enabled(&as->sys_alias, true);
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}
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}
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static void vtd_switch_address_space_all(IntelIOMMUState *s)
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{
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GHashTableIter iter;
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VTDBus *vtd_bus;
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int i;
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g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
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while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
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for (i = 0; i < X86_IOMMU_PCI_DEVFN_MAX; i++) {
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if (!vtd_bus->dev_as[i]) {
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continue;
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}
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vtd_switch_address_space(vtd_bus->dev_as[i]);
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}
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}
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}
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/* Handle Translation Enable/Disable */
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/* Handle Translation Enable/Disable */
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static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
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static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
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{
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{
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@ -2872,6 +2981,10 @@ static void vtd_init(IntelIOMMUState *s)
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s->ecap |= VTD_ECAP_DT;
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s->ecap |= VTD_ECAP_DT;
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}
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}
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if (x86_iommu->pt_supported) {
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s->ecap |= VTD_ECAP_PT;
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}
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if (s->caching_mode) {
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if (s->caching_mode) {
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s->cap |= VTD_CAP_CM;
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s->cap |= VTD_CAP_CM;
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}
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}
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@ -187,6 +187,7 @@
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/* Interrupt Remapping support */
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/* Interrupt Remapping support */
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#define VTD_ECAP_IR (1ULL << 3)
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#define VTD_ECAP_IR (1ULL << 3)
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#define VTD_ECAP_EIM (1ULL << 4)
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#define VTD_ECAP_EIM (1ULL << 4)
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#define VTD_ECAP_PT (1ULL << 6)
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#define VTD_ECAP_MHMV (15ULL << 20)
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#define VTD_ECAP_MHMV (15ULL << 20)
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/* CAP_REG */
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/* CAP_REG */
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@ -38,6 +38,8 @@ vtd_page_walk_skip_perm(uint64_t iova, uint64_t next) "Page walk skip iova 0x%"P
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vtd_page_walk_skip_reserve(uint64_t iova, uint64_t next) "Page walk skip iova 0x%"PRIx64" - 0x%"PRIx64" due to rsrv set"
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vtd_page_walk_skip_reserve(uint64_t iova, uint64_t next) "Page walk skip iova 0x%"PRIx64" - 0x%"PRIx64" due to rsrv set"
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vtd_switch_address_space(uint8_t bus, uint8_t slot, uint8_t fn, bool on) "Device %02x:%02x.%x switching address space (iommu enabled=%d)"
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vtd_switch_address_space(uint8_t bus, uint8_t slot, uint8_t fn, bool on) "Device %02x:%02x.%x switching address space (iommu enabled=%d)"
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vtd_as_unmap_whole(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova, uint64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64
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vtd_as_unmap_whole(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova, uint64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64
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vtd_translate_pt(uint16_t sid, uint64_t addr) "source id 0x%"PRIu16", iova 0x%"PRIx64
|
||||||
|
vtd_pt_enable_fast_path(uint16_t sid, bool success) "sid 0x%"PRIu16" %d"
|
||||||
|
|
||||||
# hw/i386/amd_iommu.c
|
# hw/i386/amd_iommu.c
|
||||||
amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr 0x%"PRIx64" + offset 0x%"PRIx32
|
amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr 0x%"PRIx64" + offset 0x%"PRIx32
|
||||||
|
|
|
@ -91,6 +91,7 @@ static void x86_iommu_realize(DeviceState *dev, Error **errp)
|
||||||
static Property x86_iommu_properties[] = {
|
static Property x86_iommu_properties[] = {
|
||||||
DEFINE_PROP_BOOL("intremap", X86IOMMUState, intr_supported, false),
|
DEFINE_PROP_BOOL("intremap", X86IOMMUState, intr_supported, false),
|
||||||
DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false),
|
DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false),
|
||||||
|
DEFINE_PROP_BOOL("pt", X86IOMMUState, pt_supported, true),
|
||||||
DEFINE_PROP_END_OF_LIST(),
|
DEFINE_PROP_END_OF_LIST(),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -74,6 +74,7 @@ struct X86IOMMUState {
|
||||||
SysBusDevice busdev;
|
SysBusDevice busdev;
|
||||||
bool intr_supported; /* Whether vIOMMU supports IR */
|
bool intr_supported; /* Whether vIOMMU supports IR */
|
||||||
bool dt_supported; /* Whether vIOMMU supports DT */
|
bool dt_supported; /* Whether vIOMMU supports DT */
|
||||||
|
bool pt_supported; /* Whether vIOMMU supports pass-through */
|
||||||
IommuType type; /* IOMMU type - AMD/Intel */
|
IommuType type; /* IOMMU type - AMD/Intel */
|
||||||
QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */
|
QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */
|
||||||
};
|
};
|
||||||
|
|
Loading…
Reference in a new issue