haraldwolff/qemu-patch-raspberry4
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ppc/pnv: Introduce a pnv_xive_block_id() helper

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When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field
overrides the hardwired chip ID in the Powerbus operations and for CAM
compares. This is typically used in the one block-per-chip configuration
to associate a unique block id number to each IC of the system.

Simplify the model with a pnv_xive_block_id() helper and remove
'tctx_chipid' which becomes useless.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-19-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2019-11-25 07:58:18 +01:00 committed by David Gibson
parent d1f2a574b9
commit dc2526e45a
2 changed files with 33 additions and 34 deletions
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64
hw/intc/pnv_xive.c
View file

@ -85,13 +85,30 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word,
return (word & ~mask) | ((value << ctz64(mask)) & mask);
}
/*
* When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID
* field overrides the hardwired chip ID in the Powerbus operations
* and for CAM compares
*/
static uint8_t pnv_xive_block_id(PnvXive *xive)
{
uint8_t blk = xive->chip->chip_id;
uint64_t cfg_val = xive->regs[PC_TCTXT_CFG >> 3];
if (cfg_val & PC_TCTXT_CHIPID_OVERRIDE) {
blk = GETFIELD(PC_TCTXT_CHIPID, cfg_val);
}
return blk;
}
/*
* Remote access to controllers. HW uses MMIOs. For now, a simple scan
* of the chips is good enough.
*
* TODO: Block scope support
*/
static PnvXive *pnv_xive_get_ic(uint8_t blk)
static PnvXive *pnv_xive_get_remote(uint8_t blk)
{
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
int i;
@ -100,7 +117,7 @@ static PnvXive *pnv_xive_get_ic(uint8_t blk)
Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
PnvXive *xive = &chip9->xive;
if (xive->chip->chip_id == blk) {
if (pnv_xive_block_id(xive) == blk) {
return xive;
}
}
@ -216,7 +233,7 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk,
/* Remote VST access */
if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) {
xive = pnv_xive_get_ic(blk);
xive = pnv_xive_get_remote(blk);
return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0;
}
@ -364,7 +381,10 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
{
PnvXive *xive = PNV_XIVE(xrtr);
if (pnv_xive_get_ic(blk) != xive) {
/*
* EAT lookups should be local to the IC
*/
if (pnv_xive_block_id(xive) != blk) {
xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
return -1;
}
@ -470,7 +490,7 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno)
{
PnvXive *xive = PNV_XIVE(xn);
uint8_t blk = xive->chip->chip_id;
uint8_t blk = pnv_xive_block_id(xive);
xive_router_notify(xn, XIVE_EAS(blk, srcno));
}
@ -834,20 +854,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset,
case PC_TCTXT_CFG:
/*
* TODO: block group support
*
* PC_TCTXT_CFG_BLKGRP_EN
* PC_TCTXT_CFG_HARD_CHIPID_BLK :
* Moves the chipid into block field for hardwired CAM compares.
* Block offset value is adjusted to 0b0..01 & ThrdId
*
* Will require changes in xive_presenter_tctx_match(). I am
* not sure how to handle that yet.
*/
/* Overrides hardwired chip ID with the chip ID field */
if (val & PC_TCTXT_CHIPID_OVERRIDE) {
xive->tctx_chipid = GETFIELD(PC_TCTXT_CHIPID, val);
}
break;
case PC_TCTXT_TRACK:
/*
@ -1656,19 +1663,20 @@ static const MemoryRegionOps pnv_xive_pc_ops = {
void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
{
XiveRouter *xrtr = XIVE_ROUTER(xive);
uint8_t blk = xive->chip->chip_id;
uint8_t blk = pnv_xive_block_id(xive);
uint8_t chip_id = xive->chip->chip_id;
uint32_t srcno0 = XIVE_EAS(blk, 0);
uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk);
XiveEAS eas;
XiveEND end;
int i;
monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0,
srcno0 + nr_ipis - 1);
monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk,
srcno0, srcno0 + nr_ipis - 1);
xive_source_pic_print_info(&xive->ipi_source, srcno0, mon);
monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0,
srcno0 + nr_ipis - 1);
monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk,
srcno0, srcno0 + nr_ipis - 1);
for (i = 0; i < nr_ipis; i++) {
if (xive_router_get_eas(xrtr, blk, i, &eas)) {
break;
@ -1678,13 +1686,13 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
}
}
monitor_printf(mon, "XIVE[%x] ENDT\n", blk);
monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk);
i = 0;
while (!xive_router_get_end(xrtr, blk, i, &end)) {
xive_end_pic_print_info(&end, i++, mon);
}
monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk);
monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk);
i = 0;
while (!xive_router_get_end(xrtr, blk, i, &end)) {
xive_end_eas_pic_print_info(&end, i++, mon);
@ -1697,12 +1705,6 @@ static void pnv_xive_reset(void *dev)
XiveSource *xsrc = &xive->ipi_source;
XiveENDSource *end_xsrc = &xive->end_source;
/*
* Use the PnvChip id to identify the XIVE interrupt controller.
* It can be overriden by configuration at runtime.
*/
xive->tctx_chipid = xive->chip->chip_id;
/* Default page size (Should be changed at runtime to 64k) */
xive->ic_shift = xive->vc_shift = xive->pc_shift = 12;

3
include/hw/ppc/pnv_xive.h
View file

@ -72,9 +72,6 @@ typedef struct PnvXive {
/* Interrupt controller registers */
uint64_t regs[0x300];
/* Can be configured by FW */
uint32_t tctx_chipid;
/*
* Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
* These are in a SRAM protected by ECC.