ppc/pnv: Introduce a pnv_xive_block_id() helper
When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field overrides the hardwired chip ID in the Powerbus operations and for CAM compares. This is typically used in the one block-per-chip configuration to associate a unique block id number to each IC of the system. Simplify the model with a pnv_xive_block_id() helper and remove 'tctx_chipid' which becomes useless. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191125065820.927-19-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -85,13 +85,30 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word,
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return (word & ~mask) | ((value << ctz64(mask)) & mask);
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}
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/*
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* When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID
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* field overrides the hardwired chip ID in the Powerbus operations
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* and for CAM compares
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*/
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static uint8_t pnv_xive_block_id(PnvXive *xive)
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{
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uint8_t blk = xive->chip->chip_id;
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uint64_t cfg_val = xive->regs[PC_TCTXT_CFG >> 3];
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if (cfg_val & PC_TCTXT_CHIPID_OVERRIDE) {
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blk = GETFIELD(PC_TCTXT_CHIPID, cfg_val);
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}
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return blk;
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}
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/*
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* Remote access to controllers. HW uses MMIOs. For now, a simple scan
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* of the chips is good enough.
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*
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* TODO: Block scope support
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*/
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static PnvXive *pnv_xive_get_ic(uint8_t blk)
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static PnvXive *pnv_xive_get_remote(uint8_t blk)
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{
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PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
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int i;
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@ -100,7 +117,7 @@ static PnvXive *pnv_xive_get_ic(uint8_t blk)
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Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
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PnvXive *xive = &chip9->xive;
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if (xive->chip->chip_id == blk) {
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if (pnv_xive_block_id(xive) == blk) {
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return xive;
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}
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}
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@ -216,7 +233,7 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk,
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/* Remote VST access */
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if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) {
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xive = pnv_xive_get_ic(blk);
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xive = pnv_xive_get_remote(blk);
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return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0;
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}
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@ -364,7 +381,10 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
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{
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PnvXive *xive = PNV_XIVE(xrtr);
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if (pnv_xive_get_ic(blk) != xive) {
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/*
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* EAT lookups should be local to the IC
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*/
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if (pnv_xive_block_id(xive) != blk) {
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xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
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return -1;
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}
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@ -470,7 +490,7 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
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static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno)
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{
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PnvXive *xive = PNV_XIVE(xn);
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uint8_t blk = xive->chip->chip_id;
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uint8_t blk = pnv_xive_block_id(xive);
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xive_router_notify(xn, XIVE_EAS(blk, srcno));
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}
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@ -834,20 +854,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset,
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case PC_TCTXT_CFG:
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/*
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* TODO: block group support
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*
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* PC_TCTXT_CFG_BLKGRP_EN
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* PC_TCTXT_CFG_HARD_CHIPID_BLK :
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* Moves the chipid into block field for hardwired CAM compares.
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* Block offset value is adjusted to 0b0..01 & ThrdId
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*
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* Will require changes in xive_presenter_tctx_match(). I am
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* not sure how to handle that yet.
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*/
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/* Overrides hardwired chip ID with the chip ID field */
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if (val & PC_TCTXT_CHIPID_OVERRIDE) {
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xive->tctx_chipid = GETFIELD(PC_TCTXT_CHIPID, val);
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}
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break;
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case PC_TCTXT_TRACK:
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/*
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@ -1656,19 +1663,20 @@ static const MemoryRegionOps pnv_xive_pc_ops = {
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void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
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{
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XiveRouter *xrtr = XIVE_ROUTER(xive);
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uint8_t blk = xive->chip->chip_id;
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uint8_t blk = pnv_xive_block_id(xive);
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uint8_t chip_id = xive->chip->chip_id;
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uint32_t srcno0 = XIVE_EAS(blk, 0);
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uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk);
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XiveEAS eas;
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XiveEND end;
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int i;
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monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0,
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srcno0 + nr_ipis - 1);
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monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk,
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srcno0, srcno0 + nr_ipis - 1);
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xive_source_pic_print_info(&xive->ipi_source, srcno0, mon);
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monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0,
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srcno0 + nr_ipis - 1);
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monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk,
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srcno0, srcno0 + nr_ipis - 1);
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for (i = 0; i < nr_ipis; i++) {
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if (xive_router_get_eas(xrtr, blk, i, &eas)) {
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break;
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@ -1678,13 +1686,13 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
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}
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}
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monitor_printf(mon, "XIVE[%x] ENDT\n", blk);
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monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk);
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i = 0;
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while (!xive_router_get_end(xrtr, blk, i, &end)) {
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xive_end_pic_print_info(&end, i++, mon);
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}
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monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk);
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monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk);
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i = 0;
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while (!xive_router_get_end(xrtr, blk, i, &end)) {
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xive_end_eas_pic_print_info(&end, i++, mon);
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@ -1697,12 +1705,6 @@ static void pnv_xive_reset(void *dev)
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XiveSource *xsrc = &xive->ipi_source;
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XiveENDSource *end_xsrc = &xive->end_source;
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/*
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* Use the PnvChip id to identify the XIVE interrupt controller.
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* It can be overriden by configuration at runtime.
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*/
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xive->tctx_chipid = xive->chip->chip_id;
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/* Default page size (Should be changed at runtime to 64k) */
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xive->ic_shift = xive->vc_shift = xive->pc_shift = 12;
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@ -72,9 +72,6 @@ typedef struct PnvXive {
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/* Interrupt controller registers */
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uint64_t regs[0x300];
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/* Can be configured by FW */
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uint32_t tctx_chipid;
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/*
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* Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
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* These are in a SRAM protected by ECC.
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