hw/stellaris: Add support for RCC2 register
Add support for the RCC2 register on Fury class devices. Based on a patch by Vijay Kumar. Signed-off-by: Engin AYDOGAN <engin@bzzzt.biz> [Peter Maydell: fixed comment typos, minor cleanup of unreachable code] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -332,6 +332,7 @@ typedef struct {
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uint32_t int_mask;
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uint32_t resc;
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uint32_t rcc;
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uint32_t rcc2;
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uint32_t rcgc[3];
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uint32_t scgc[3];
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uint32_t dcgc[3];
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@ -386,6 +387,32 @@ static uint32_t pllcfg_fury[16] = {
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0xb11c /* 8.192 Mhz */
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};
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#define DID0_VER_MASK 0x70000000
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#define DID0_VER_0 0x00000000
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#define DID0_VER_1 0x10000000
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#define DID0_CLASS_MASK 0x00FF0000
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#define DID0_CLASS_SANDSTORM 0x00000000
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#define DID0_CLASS_FURY 0x00010000
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static int ssys_board_class(const ssys_state *s)
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{
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uint32_t did0 = s->board->did0;
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switch (did0 & DID0_VER_MASK) {
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case DID0_VER_0:
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return DID0_CLASS_SANDSTORM;
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case DID0_VER_1:
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switch (did0 & DID0_CLASS_MASK) {
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case DID0_CLASS_SANDSTORM:
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case DID0_CLASS_FURY:
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return did0 & DID0_CLASS_MASK;
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}
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/* for unknown classes, fall through */
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default:
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hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
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}
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}
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static uint32_t ssys_read(void *opaque, target_phys_addr_t offset)
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{
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ssys_state *s = (ssys_state *)opaque;
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@ -429,12 +456,18 @@ static uint32_t ssys_read(void *opaque, target_phys_addr_t offset)
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{
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int xtal;
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xtal = (s->rcc >> 6) & 0xf;
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if (s->board->did0 & (1 << 16)) {
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switch (ssys_board_class(s)) {
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case DID0_CLASS_FURY:
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return pllcfg_fury[xtal];
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} else {
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case DID0_CLASS_SANDSTORM:
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return pllcfg_sandstorm[xtal];
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default:
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hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
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return 0;
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}
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}
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case 0x070: /* RCC2 */
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return s->rcc2;
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case 0x100: /* RCGC0 */
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return s->rcgc[0];
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case 0x104: /* RCGC1 */
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@ -467,9 +500,21 @@ static uint32_t ssys_read(void *opaque, target_phys_addr_t offset)
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}
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}
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static bool ssys_use_rcc2(ssys_state *s)
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{
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return (s->rcc2 >> 31) & 0x1;
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}
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/*
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* Caculate the sys. clock period in ms.
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*/
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static void ssys_calculate_system_clock(ssys_state *s)
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{
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if (ssys_use_rcc2(s)) {
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system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
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} else {
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system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
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}
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}
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static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value)
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@ -505,6 +550,18 @@ static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value)
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s->rcc = value;
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ssys_calculate_system_clock(s);
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break;
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case 0x070: /* RCC2 */
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if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
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break;
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}
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if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
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/* PLL enable. */
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s->int_status |= (1 << 6);
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}
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s->rcc2 = value;
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ssys_calculate_system_clock(s);
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break;
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case 0x100: /* RCGC0 */
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s->rcgc[0] = value;
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break;
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@ -562,6 +619,12 @@ static void ssys_reset(void *opaque)
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s->pborctl = 0x7ffd;
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s->rcc = 0x078e3ac0;
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if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
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s->rcc2 = 0;
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} else {
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s->rcc2 = 0x07802810;
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}
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s->rcgc[0] = 1;
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s->scgc[0] = 1;
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s->dcgc[0] = 1;
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@ -578,7 +641,7 @@ static int stellaris_sys_post_load(void *opaque, int version_id)
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static const VMStateDescription vmstate_stellaris_sys = {
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.name = "stellaris_sys",
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.version_id = 1,
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = stellaris_sys_post_load,
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@ -589,6 +652,7 @@ static const VMStateDescription vmstate_stellaris_sys = {
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VMSTATE_UINT32(int_status, ssys_state),
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VMSTATE_UINT32(resc, ssys_state),
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VMSTATE_UINT32(rcc, ssys_state),
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VMSTATE_UINT32_V(rcc2, ssys_state, 2),
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VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
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VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
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VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
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