target-arm: Fix implementation of TLB invalidate operations
Fix some bugs in the implementation of the TLB invalidate operations on ARM: * the 'invalidate all' op was not passing flush_global=1 to tlb_flush(); this doesn't have a practical effect since tlb_flush() currently ignores that argument, but is semantically incorrect * 'invalidate by address for all ASIDs' was implemented as flushing the whole TLB, which invalidates much more than strictly necessary. Use tlb_flush_page() instead. We also annotate the ops with the ARM ARM official acronyms. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1610,18 +1610,17 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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break;
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break;
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case 8: /* MMU TLB control. */
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case 8: /* MMU TLB control. */
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switch (op2) {
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switch (op2) {
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case 0: /* Invalidate all. */
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case 0: /* Invalidate all (TLBIALL) */
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tlb_flush(env, 0);
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tlb_flush(env, 1);
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break;
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break;
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case 1: /* Invalidate single TLB entry. */
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case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
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tlb_flush_page(env, val & TARGET_PAGE_MASK);
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tlb_flush_page(env, val & TARGET_PAGE_MASK);
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break;
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break;
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case 2: /* Invalidate on ASID. */
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case 2: /* Invalidate by ASID (TLBIASID) */
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tlb_flush(env, val == 0);
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tlb_flush(env, val == 0);
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break;
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break;
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case 3: /* Invalidate single entry on MVA. */
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case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
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/* ??? This is like case 1, but ignores ASID. */
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tlb_flush_page(env, val & TARGET_PAGE_MASK);
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tlb_flush(env, 1);
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break;
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break;
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default:
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default:
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goto bad_reg;
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goto bad_reg;
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