target/arm: Add support for FEAT_DIT, Data Independent Timing
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required feature for ARMv8.4. Since virtual machine execution is largely nondeterministic and TCG is outside of the security domain, it's implemented as a NOP. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210208065700.19454-2-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1243,6 +1243,7 @@ void pmu_init(ARMCPU *cpu);
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#define CPSR_IT_2_7 (0xfc00U)
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#define CPSR_GE (0xfU << 16)
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#define CPSR_IL (1U << 20)
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#define CPSR_DIT (1U << 21)
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#define CPSR_PAN (1U << 22)
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#define CPSR_J (1U << 24)
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#define CPSR_IT_0_1 (3U << 25)
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@ -1310,6 +1311,7 @@ void pmu_init(ARMCPU *cpu);
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#define PSTATE_SS (1U << 21)
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#define PSTATE_PAN (1U << 22)
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#define PSTATE_UAO (1U << 23)
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#define PSTATE_DIT (1U << 24)
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#define PSTATE_TCO (1U << 25)
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#define PSTATE_V (1U << 28)
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#define PSTATE_C (1U << 29)
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@ -3876,6 +3878,11 @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
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return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
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}
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static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
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{
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return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
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}
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/*
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* 64-bit feature tests via id registers.
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*/
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@ -4125,6 +4132,11 @@ static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
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}
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static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
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}
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/*
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* Feature tests for "does this exist in either 32-bit or 64-bit?"
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*/
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@ -4431,6 +4431,24 @@ static const ARMCPRegInfo uao_reginfo = {
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.readfn = aa64_uao_read, .writefn = aa64_uao_write
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};
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static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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return env->pstate & PSTATE_DIT;
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}
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static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT);
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}
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static const ARMCPRegInfo dit_reginfo = {
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.name = "DIT", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5,
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.type = ARM_CP_NO_RAW, .access = PL0_RW,
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.readfn = aa64_dit_read, .writefn = aa64_dit_write
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};
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static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
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const ARMCPRegInfo *ri,
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bool isread)
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@ -8224,6 +8242,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_one_arm_cp_reg(cpu, &uao_reginfo);
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}
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if (cpu_isar_feature(aa64_dit, cpu)) {
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define_one_arm_cp_reg(cpu, &dit_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
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define_arm_cp_regs(cpu, vhe_reginfo);
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}
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@ -1228,6 +1228,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
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if (isar_feature_aa32_pan(id)) {
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valid |= CPSR_PAN;
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}
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if (isar_feature_aa32_dit(id)) {
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valid |= CPSR_DIT;
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}
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return valid;
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}
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@ -1246,6 +1249,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
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if (isar_feature_aa64_uao(id)) {
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valid |= PSTATE_UAO;
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}
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if (isar_feature_aa64_dit(id)) {
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valid |= PSTATE_DIT;
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}
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if (isar_feature_aa64_mte(id)) {
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valid |= PSTATE_TCO;
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}
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@ -1700,6 +1700,18 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
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tcg_temp_free_i32(t1);
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break;
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case 0x1a: /* DIT */
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if (!dc_isar_feature(aa64_dit, s)) {
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goto do_unallocated;
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}
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if (crm & 1) {
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set_pstate_bits(PSTATE_DIT);
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} else {
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clear_pstate_bits(PSTATE_DIT);
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}
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/* There's no need to rebuild hflags because DIT is a nop */
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break;
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case 0x1e: /* DAIFSet */
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t1 = tcg_const_i32(crm);
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gen_helper_msr_i_daifset(cpu_env, t1);
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