target/xtensa: add DFPU option
Double precision floating point unit is a FPU implementation different from the FPU2000 in the following ways: - it may be configured with only single or with both single and double precision operations support; - it may be configured with division and square root opcodes; - FSR register accumulates inValid, division by Zero, Overflow, Underflow and Inexact result flags of operations; - QNaNs and SNaNs are handled properly; - NaN propagation rules are different. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -52,6 +52,8 @@ enum {
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XTENSA_OPTION_COPROCESSOR,
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XTENSA_OPTION_COPROCESSOR,
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XTENSA_OPTION_BOOLEAN,
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XTENSA_OPTION_BOOLEAN,
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XTENSA_OPTION_FP_COPROCESSOR,
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XTENSA_OPTION_FP_COPROCESSOR,
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XTENSA_OPTION_DFP_COPROCESSOR,
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XTENSA_OPTION_DFPU_SINGLE_ONLY,
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XTENSA_OPTION_MP_SYNCHRO,
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XTENSA_OPTION_MP_SYNCHRO,
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XTENSA_OPTION_CONDITIONAL_STORE,
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XTENSA_OPTION_CONDITIONAL_STORE,
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XTENSA_OPTION_ATOMCTL,
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XTENSA_OPTION_ATOMCTL,
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@ -39,6 +39,26 @@
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#define XCHAL_HAVE_DEPBITS 0
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#define XCHAL_HAVE_DEPBITS 0
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#endif
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#endif
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#ifndef XCHAL_HAVE_DFP
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#define XCHAL_HAVE_DFP 0
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#endif
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#ifndef XCHAL_HAVE_DFPU_SINGLE_ONLY
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#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0
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#endif
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#ifndef XCHAL_HAVE_DFPU_SINGLE_DOUBLE
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#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE XCHAL_HAVE_DFP
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#endif
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/*
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* We need to know the type of FP unit, not only its precision.
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* Unfortunately XCHAL macros don't tell this explicitly.
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*/
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#define XCHAL_HAVE_DFPU (XCHAL_HAVE_DFP || \
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XCHAL_HAVE_DFPU_SINGLE_ONLY || \
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XCHAL_HAVE_DFPU_SINGLE_DOUBLE)
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#ifndef XCHAL_HAVE_DIV32
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#ifndef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 0
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#define XCHAL_HAVE_DIV32 0
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#endif
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#endif
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@ -99,6 +119,9 @@
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XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
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XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
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XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
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XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
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XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
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XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
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XCHAL_OPTION(XCHAL_HAVE_DFPU, XTENSA_OPTION_DFP_COPROCESSOR) | \
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XCHAL_OPTION(XCHAL_HAVE_DFPU_SINGLE_ONLY, \
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XTENSA_OPTION_DFPU_SINGLE_ONLY) | \
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XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
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XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
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XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
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XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
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XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
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XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
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