hw/dma: sifive_pdma: reset Next* registers when Control.claim is set
Setting Control.claim clears all of the chanel's Next registers. This is effective only when Control.claim is set from 0 to 1. Signed-off-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210912130553.179501-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -54,6 +54,13 @@
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#define DMA_EXEC_DST 0x110
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#define DMA_EXEC_SRC 0x118
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/*
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* FU540/FU740 docs are incorrect with NextConfig.wsize/rsize reset values.
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* The reset values tested on Unleashed/Unmatched boards are 6 instead of 0.
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*/
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#define CONFIG_WRSZ_DEFAULT 6
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#define CONFIG_RDSZ_DEFAULT 6
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enum dma_chan_state {
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DMA_CHAN_STATE_IDLE,
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DMA_CHAN_STATE_STARTED,
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@ -221,6 +228,7 @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
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{
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SiFivePDMAState *s = opaque;
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int ch = SIFIVE_PDMA_CHAN_NO(offset);
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bool claimed;
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if (ch >= SIFIVE_PDMA_CHANS) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
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@ -231,6 +239,17 @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
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offset &= 0xfff;
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switch (offset) {
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case DMA_CONTROL:
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claimed = !!s->chan[ch].control & CONTROL_CLAIM;
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if (!claimed && (value & CONTROL_CLAIM)) {
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/* reset Next* registers */
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s->chan[ch].next_config = (CONFIG_RDSZ_DEFAULT << CONFIG_RDSZ_SHIFT) |
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(CONFIG_WRSZ_DEFAULT << CONFIG_WRSZ_SHIFT);
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s->chan[ch].next_bytes = 0;
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s->chan[ch].next_dst = 0;
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s->chan[ch].next_src = 0;
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}
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s->chan[ch].control = value;
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if (value & CONTROL_RUN) {
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