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target-arm: Use the right MMU index in arm_regime_using_lpae_format

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arm_regime_using_lpae_format checks whether the LPAE extension is used
for stage 1 translation regimes. MMU indexes not exclusively of a stage 1
regime won't work with this method.

In case of ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1, offset these values
by ARMMMUIdx_S1NSE0 to get the right index indicating a stage 1
translation regime.

Rename also the function to arm_s1_regime_using_lpae_format and update
the comments to reflect the change.

Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
Message-id: 1452854262-19550-1-git-send-email-a.rigo@virtualopensystems.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alvise Rigo 2016-01-15 11:37:42 +01:00 committed by Peter Maydell
parent f02ccf5369
commit deb2db996c
3 changed files with 12 additions and 7 deletions
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12
target-arm/helper.c
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@ -5996,11 +5996,15 @@ static inline bool regime_using_lpae_format(CPUARMState *env,
return false; return false;
} }
/* Returns true if the translation regime is using LPAE format page tables. /* Returns true if the stage 1 translation regime is using LPAE format page
* Used when raising alignment exceptions, whose FSR changes depending on * tables. Used when raising alignment exceptions, whose FSR changes depending
* whether the long or short descriptor format is in use. */ * on whether the long or short descriptor format is in use. */
bool arm_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
{ {
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
mmu_idx += ARMMMUIdx_S1NSE0;
}
return regime_using_lpae_format(env, mmu_idx); return regime_using_lpae_format(env, mmu_idx);
} }

5
target-arm/internals.h
View file

@ -441,8 +441,9 @@ struct ARMMMUFaultInfo {
bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,
uint32_t *fsr, ARMMMUFaultInfo *fi); uint32_t *fsr, ARMMMUFaultInfo *fi);
/* Return true if the translation regime is using LPAE format page tables */ /* Return true if the stage 1 translation regime is using LPAE format page
bool arm_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); * tables */
bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
/* Raise a data fault alignment exception for the specified virtual address */ /* Raise a data fault alignment exception for the specified virtual address */
void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,

2
target-arm/op_helper.c
View file

@ -149,7 +149,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,
/* the DFSR for an alignment fault depends on whether we're using /* the DFSR for an alignment fault depends on whether we're using
* the LPAE long descriptor format, or the short descriptor format * the LPAE long descriptor format, or the short descriptor format
*/ */
if (arm_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
env->exception.fsr = 0x21; env->exception.fsr = 0x21;
} else { } else {
env->exception.fsr = 0x1; env->exception.fsr = 0x1;