acpi/pcihp: Convert debug printf()s to trace events
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190402161900.7374-3-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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@ -37,14 +37,7 @@
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_bus.h"
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#include "qapi/error.h"
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#include "qapi/error.h"
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#include "qom/qom-qobject.h"
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#include "qom/qom-qobject.h"
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#include "trace.h"
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//#define DEBUG
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#ifdef DEBUG
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# define ACPI_PCIHP_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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#else
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# define ACPI_PCIHP_DPRINTF(format, ...) do { } while (0)
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#endif
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#define ACPI_PCIHP_ADDR 0xae00
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#define ACPI_PCIHP_ADDR 0xae00
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#define ACPI_PCIHP_SIZE 0x0014
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#define ACPI_PCIHP_SIZE 0x0014
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@ -306,23 +299,23 @@ static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
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if (!s->legacy_piix) {
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if (!s->legacy_piix) {
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s->acpi_pcihp_pci_status[bsel].up = 0;
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s->acpi_pcihp_pci_status[bsel].up = 0;
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}
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}
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ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
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trace_acpi_pci_up_read(val);
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break;
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break;
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case PCI_DOWN_BASE:
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case PCI_DOWN_BASE:
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val = s->acpi_pcihp_pci_status[bsel].down;
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val = s->acpi_pcihp_pci_status[bsel].down;
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ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
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trace_acpi_pci_down_read(val);
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break;
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break;
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case PCI_EJ_BASE:
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case PCI_EJ_BASE:
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/* No feature defined yet */
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/* No feature defined yet */
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ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
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trace_acpi_pci_features_read(val);
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break;
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break;
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case PCI_RMV_BASE:
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case PCI_RMV_BASE:
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val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
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val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
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ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
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trace_acpi_pci_rmv_read(val);
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break;
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break;
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case PCI_SEL_BASE:
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case PCI_SEL_BASE:
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val = s->hotplug_select;
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val = s->hotplug_select;
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ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
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trace_acpi_pci_sel_read(val);
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default:
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default:
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break;
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break;
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}
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}
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@ -340,13 +333,11 @@ static void pci_write(void *opaque, hwaddr addr, uint64_t data,
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break;
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break;
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}
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}
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acpi_pcihp_eject_slot(s, s->hotplug_select, data);
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acpi_pcihp_eject_slot(s, s->hotplug_select, data);
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ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
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trace_acpi_pci_ej_write(addr, data);
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addr, data);
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break;
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break;
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case PCI_SEL_BASE:
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case PCI_SEL_BASE:
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s->hotplug_select = s->legacy_piix ? ACPI_PCIHP_BSEL_DEFAULT : data;
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s->hotplug_select = s->legacy_piix ? ACPI_PCIHP_BSEL_DEFAULT : data;
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ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
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trace_acpi_pci_sel_write(addr, data);
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addr, data);
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default:
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default:
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break;
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break;
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}
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}
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@ -31,6 +31,15 @@ cpuhp_acpi_ejecting_cpu(uint32_t idx) "0x%"PRIx32
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cpuhp_acpi_write_ost_ev(uint32_t slot, uint32_t ev) "idx[0x%"PRIx32"] OST EVENT: 0x%"PRIx32
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cpuhp_acpi_write_ost_ev(uint32_t slot, uint32_t ev) "idx[0x%"PRIx32"] OST EVENT: 0x%"PRIx32
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cpuhp_acpi_write_ost_status(uint32_t slot, uint32_t st) "idx[0x%"PRIx32"] OST STATUS: 0x%"PRIx32
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cpuhp_acpi_write_ost_status(uint32_t slot, uint32_t st) "idx[0x%"PRIx32"] OST STATUS: 0x%"PRIx32
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# pcihp.c
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acpi_pci_up_read(uint32_t val) "%" PRIu32
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acpi_pci_down_read(uint32_t val) "%" PRIu32
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acpi_pci_features_read(uint32_t val) "%" PRIu32
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acpi_pci_rmv_read(uint32_t val) "%" PRIu32
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acpi_pci_sel_read(uint32_t val) "%" PRIu32
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acpi_pci_ej_write(uint64_t addr, uint64_t data) "0x%" PRIx64 " <== %" PRIu64
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acpi_pci_sel_write(uint64_t addr, uint64_t data) "0x%" PRIx64 " <== %" PRIu64
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# piix4.c
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# piix4.c
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piix4_gpe_readb(uint64_t addr, unsigned width, uint64_t val) "addr: 0x%" PRIx64 " width: %d ==> 0x%" PRIx64
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piix4_gpe_readb(uint64_t addr, unsigned width, uint64_t val) "addr: 0x%" PRIx64 " width: %d ==> 0x%" PRIx64
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piix4_gpe_writeb(uint64_t addr, unsigned width, uint64_t val) "addr: 0x%" PRIx64 " width: %d <== 0x%" PRIx64
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piix4_gpe_writeb(uint64_t addr, unsigned width, uint64_t val) "addr: 0x%" PRIx64 " width: %d <== 0x%" PRIx64
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