haraldwolff/qemu-patch-raspberry4
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pseries: Fix some small errors in XICS logic

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Under certain circumstances the emulation for the pseries "XICS" interrupt
controller was clearing a pending interrupt from the XISR register, without
also clearing the corresponding priority variable.  This will cause
problems later when can trigger sanity checks in the under-development
in-kernel XICS implementation.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
David Gibson 2013-04-07 19:08:21 +00:00 committed by Alexander Graf
parent 702763fa32
commit e03c902cb6
1 changed files with 2 additions and 0 deletions
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2
hw/ppc/xics.c
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@ -101,6 +101,7 @@ static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
if (XISR(ss) && (cppr <= ss->pending_priority)) {
old_xisr = XISR(ss);
ss->xirr &= ~XISR_MASK; /* Clear XISR */
ss->pending_priority = 0xff;
qemu_irq_lower(ss->output);
ics_reject(icp->ics, old_xisr);
}
@ -127,6 +128,7 @@ static uint32_t icp_accept(struct icp_server_state *ss)
qemu_irq_lower(ss->output);
ss->xirr = ss->pending_priority << 24;
ss->pending_priority = 0xff;
trace_xics_icp_accept(xirr, ss->xirr);