vmstate: port ppce500_pci
Signed-off-by: Juan Quintela <quintela@redhat.com>
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@ -216,56 +216,49 @@ static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
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qemu_set_irq(pic[irq_num], level);
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}
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static void ppce500_pci_save(QEMUFile *f, void *opaque)
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{
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PPCE500PCIState *controller = opaque;
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int i;
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pci_device_save(controller->pci_dev, f);
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for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
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qemu_put_be32s(f, &controller->pob[i].potar);
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qemu_put_be32s(f, &controller->pob[i].potear);
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qemu_put_be32s(f, &controller->pob[i].powbar);
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qemu_put_be32s(f, &controller->pob[i].powar);
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static const VMStateDescription vmstate_pci_outbound = {
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.name = "pci_outbound",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(potar, struct pci_outbound),
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VMSTATE_UINT32(potear, struct pci_outbound),
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VMSTATE_UINT32(powbar, struct pci_outbound),
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VMSTATE_UINT32(powar, struct pci_outbound),
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VMSTATE_END_OF_LIST()
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}
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};
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for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
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qemu_put_be32s(f, &controller->pib[i].pitar);
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qemu_put_be32s(f, &controller->pib[i].piwbar);
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qemu_put_be32s(f, &controller->pib[i].piwbear);
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qemu_put_be32s(f, &controller->pib[i].piwar);
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static const VMStateDescription vmstate_pci_inbound = {
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.name = "pci_inbound",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(pitar, struct pci_inbound),
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VMSTATE_UINT32(piwbar, struct pci_inbound),
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VMSTATE_UINT32(piwbear, struct pci_inbound),
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VMSTATE_UINT32(piwar, struct pci_inbound),
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VMSTATE_END_OF_LIST()
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}
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qemu_put_be32s(f, &controller->gasket_time);
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}
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};
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static int ppce500_pci_load(QEMUFile *f, void *opaque, int version_id)
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{
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PPCE500PCIState *controller = opaque;
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int i;
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if (version_id != 1)
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return -EINVAL;
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pci_device_load(controller->pci_dev, f);
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for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
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qemu_get_be32s(f, &controller->pob[i].potar);
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qemu_get_be32s(f, &controller->pob[i].potear);
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qemu_get_be32s(f, &controller->pob[i].powbar);
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qemu_get_be32s(f, &controller->pob[i].powar);
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static const VMStateDescription vmstate_ppce500_pci = {
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.name = "ppce500_pci",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPCE500PCIState),
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VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
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vmstate_pci_outbound, struct pci_outbound),
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VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
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vmstate_pci_outbound, struct pci_inbound),
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VMSTATE_UINT32(gasket_time, PPCE500PCIState),
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VMSTATE_END_OF_LIST()
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}
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for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
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qemu_get_be32s(f, &controller->pib[i].pitar);
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qemu_get_be32s(f, &controller->pib[i].piwbar);
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qemu_get_be32s(f, &controller->pib[i].piwbear);
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qemu_get_be32s(f, &controller->pib[i].piwar);
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}
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qemu_get_be32s(f, &controller->gasket_time);
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return 0;
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}
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};
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PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
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{
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@ -314,8 +307,8 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
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PCIE500_REG_SIZE, index);
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/* XXX load/save code not tested. */
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register_savevm(&d->qdev, "ppce500_pci", ppce500_pci_id++,
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1, ppce500_pci_save, ppce500_pci_load, controller);
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vmstate_register(&d->qdev, ppce500_pci_id++, &vmstate_ppce500_pci,
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controller);
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return controller->pci_state.bus;
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