ppc: Implement bcds. instruction
bcds.: Decimal shift. Given two registers vra and vrb, this instruction shift the vrb value by vra bits into the result register. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -393,6 +393,7 @@ DEF_HELPER_3(bcdcfsq, i32, avr, avr, i32)
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DEF_HELPER_3(bcdctsq, i32, avr, avr, i32)
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DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
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DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
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DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
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DEF_HELPER_2(xsadddp, void, env, i32)
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DEF_HELPER_2(xsaddqp, void, env, i32)
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@ -3062,6 +3062,46 @@ uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
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return bcd_cmp_zero(r);
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}
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uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
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{
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int cr;
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#if defined(HOST_WORDS_BIGENDIAN)
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int i = a->s8[7];
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#else
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int i = a->s8[8];
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#endif
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bool ox_flag = false;
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int sgnb = bcd_get_sgn(b);
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ppc_avr_t ret = *b;
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ret.u64[LO_IDX] &= ~0xf;
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if (bcd_is_valid(b) == false) {
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return CRF_SO;
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}
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if (unlikely(i > 31)) {
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i = 31;
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} else if (unlikely(i < -31)) {
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i = -31;
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}
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if (i > 0) {
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ulshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], i * 4, &ox_flag);
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} else {
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urshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], -i * 4);
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}
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bcd_put_digit(&ret, bcd_preferred_sgn(sgnb, ps), 0);
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*r = ret;
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cr = bcd_cmp_zero(r);
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if (ox_flag) {
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cr |= CRF_SO;
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}
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return cr;
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}
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void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
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{
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int i;
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@ -1016,6 +1016,7 @@ GEN_BCD2(bcdcfsq)
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GEN_BCD2(bcdctsq)
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GEN_BCD2(bcdsetsgn)
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GEN_BCD(bcdcpsgn);
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GEN_BCD(bcds);
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static void gen_xpnd04_1(DisasContext *ctx)
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{
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@ -1090,6 +1091,8 @@ GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
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bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
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GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
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bcdcpsgn, PPC_NONE, PPC2_ISA300)
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GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
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bcds, PPC_NONE, PPC2_ISA300)
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static void gen_vsbox(DisasContext *ctx)
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{
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@ -62,7 +62,8 @@ GEN_VXFORM_207(vaddudm, 0, 3),
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GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM(vsubuwm, 0, 18),
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GEN_VXFORM_207(vsubudm, 0, 19),
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GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300),
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GEN_VXFORM_300(bcds, 0, 27),
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GEN_VXFORM(vmaxub, 1, 0),
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GEN_VXFORM(vmaxuh, 1, 1),
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GEN_VXFORM(vmaxuw, 1, 2),
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