Move the MIPS CPU timer in a seperate file, by Alec Voropay.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2225 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -357,7 +357,7 @@ VL_OBJS+= grackle_pci.o prep_pci.o unin_pci.o
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DEFINES += -DHAS_AUDIO
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endif
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ifeq ($(TARGET_ARCH), mips)
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VL_OBJS+= mips_r4k.o dma.o vga.o serial.o i8254.o i8259.o ide.o
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VL_OBJS+= mips_r4k.o mips_timer.o dma.o vga.o serial.o i8254.o i8259.o ide.o
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#VL_OBJS+= #pckbd.o fdc.o m48t59.o
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endif
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ifeq ($(TARGET_BASE_ARCH), sparc)
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@ -1,3 +1,12 @@
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/*
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* QEMU/MIPS pseudo-board
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*
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* emulates a simple machine with ISA-like bus.
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* ISA IO space mapped to the 0x14000000 (PHYS) and
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* ISA memory at the 0x10000000 (PHYS, 16Mb in size).
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* All peripherial devices are attached to this "bus" with
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* the standard PC ISA addresses.
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*/
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#include "vl.h"
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#define BIOS_FILENAME "mips_bios.bin"
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@ -13,8 +22,10 @@ static const int ide_irq[2] = { 14, 15 };
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extern FILE *logfile;
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static PITState *pit;
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static PITState *pit; /* PIT i8254 */
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/*i8254 PIT is attached to the IRQ0 at PIC i8259 */
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/*The PIC is attached to the MIPS CPU INT0 pin */
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static void pic_irq_request(void *opaque, int level)
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{
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CPUState *env = first_cpu;
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@ -27,89 +38,6 @@ static void pic_irq_request(void *opaque, int level)
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}
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}
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void cpu_mips_irqctrl_init (void)
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{
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}
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/* XXX: do not use a global */
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uint32_t cpu_mips_get_random (CPUState *env)
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{
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static uint32_t seed = 0;
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uint32_t idx;
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seed = seed * 314159 + 1;
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idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
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return idx;
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}
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/* MIPS R4K timer */
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uint32_t cpu_mips_get_count (CPUState *env)
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{
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return env->CP0_Count +
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(uint32_t)muldiv64(qemu_get_clock(vm_clock),
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100 * 1000 * 1000, ticks_per_sec);
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}
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static void cpu_mips_update_count (CPUState *env, uint32_t count,
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uint32_t compare)
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{
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uint64_t now, next;
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uint32_t tmp;
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tmp = count;
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if (count == compare)
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tmp++;
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now = qemu_get_clock(vm_clock);
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next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
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if (next == now)
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next++;
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#if 0
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if (logfile) {
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fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
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__func__, now, count, compare, next - now);
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}
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#endif
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/* Store new count and compare registers */
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env->CP0_Compare = compare;
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env->CP0_Count =
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count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
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/* Adjust timer */
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qemu_mod_timer(env->timer, next);
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}
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void cpu_mips_store_count (CPUState *env, uint32_t value)
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{
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cpu_mips_update_count(env, value, env->CP0_Compare);
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}
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void cpu_mips_store_compare (CPUState *env, uint32_t value)
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{
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cpu_mips_update_count(env, cpu_mips_get_count(env), value);
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env->CP0_Cause &= ~0x00008000;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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static void mips_timer_cb (void *opaque)
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{
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CPUState *env;
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env = opaque;
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#if 0
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if (logfile) {
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fprintf(logfile, "%s\n", __func__);
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}
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#endif
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cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
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env->CP0_Cause |= 0x00008000;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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void cpu_mips_clock_init (CPUState *env)
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{
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env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
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env->CP0_Compare = 0;
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cpu_mips_update_count(env, 1, 0);
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}
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static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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@ -247,7 +175,7 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
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env->initrd_filename = initrd_filename;
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}
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/* Init internal devices */
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/* Init CPU internal devices */
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cpu_mips_clock_init(env);
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cpu_mips_irqctrl_init();
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85
hw/mips_timer.c
Normal file
85
hw/mips_timer.c
Normal file
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@ -0,0 +1,85 @@
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#include "vl.h"
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void cpu_mips_irqctrl_init (void)
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{
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}
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/* XXX: do not use a global */
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uint32_t cpu_mips_get_random (CPUState *env)
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{
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static uint32_t seed = 0;
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uint32_t idx;
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seed = seed * 314159 + 1;
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idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
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return idx;
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}
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/* MIPS R4K timer */
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uint32_t cpu_mips_get_count (CPUState *env)
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{
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return env->CP0_Count +
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(uint32_t)muldiv64(qemu_get_clock(vm_clock),
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100 * 1000 * 1000, ticks_per_sec);
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}
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static void cpu_mips_update_count (CPUState *env, uint32_t count,
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uint32_t compare)
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{
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uint64_t now, next;
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uint32_t tmp;
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tmp = count;
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if (count == compare)
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tmp++;
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now = qemu_get_clock(vm_clock);
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next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
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if (next == now)
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next++;
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#if 0
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if (logfile) {
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fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
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__func__, now, count, compare, next - now);
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}
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#endif
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/* Store new count and compare registers */
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env->CP0_Compare = compare;
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env->CP0_Count =
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count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
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/* Adjust timer */
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qemu_mod_timer(env->timer, next);
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}
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void cpu_mips_store_count (CPUState *env, uint32_t value)
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{
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cpu_mips_update_count(env, value, env->CP0_Compare);
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}
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void cpu_mips_store_compare (CPUState *env, uint32_t value)
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{
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cpu_mips_update_count(env, cpu_mips_get_count(env), value);
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env->CP0_Cause &= ~0x00008000;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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static void mips_timer_cb (void *opaque)
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{
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CPUState *env;
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env = opaque;
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#if 0
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if (logfile) {
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fprintf(logfile, "%s\n", __func__);
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}
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#endif
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cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
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env->CP0_Cause |= 0x00008000;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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void cpu_mips_clock_init (CPUState *env)
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{
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env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
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env->CP0_Compare = 0;
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cpu_mips_update_count(env, 1, 0);
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}
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