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target/openrisc: Convert dec_logic

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Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2018-02-20 10:20:06 -08:00
parent 99d863d6d6
commit e20c2592bc
2 changed files with 32 additions and 36 deletions
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6
target/openrisc/insns.decode
View file

@ -20,6 +20,7 @@
&dab d a b
&da d a
&ab a b
&dal d a l
####
# System Instructions
@ -130,3 +131,8 @@ l_mac 110001 ----- a:5 b:5 ------- 0001
l_macu 110001 ----- a:5 b:5 ------- 0011
l_msb 110001 ----- a:5 b:5 ------- 0010
l_msbu 110001 ----- a:5 b:5 ------- 0100
l_slli 101110 d:5 a:5 -------- 00 l:6
l_srli 101110 d:5 a:5 -------- 01 l:6
l_srai 101110 d:5 a:5 -------- 10 l:6
l_rori 101110 d:5 a:5 -------- 11 l:6

62
target/openrisc/translate.c
View file

@ -998,42 +998,36 @@ static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn)
return true;
}
static void dec_logic(DisasContext *dc, uint32_t insn)
static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn)
{
uint32_t op0;
uint32_t rd, ra, L6, S6;
op0 = extract32(insn, 6, 2);
rd = extract32(insn, 21, 5);
ra = extract32(insn, 16, 5);
L6 = extract32(insn, 0, 6);
S6 = L6 & (TARGET_LONG_BITS - 1);
LOG_DIS("l.slli r%d, r%d, %d\n", a->d, a->a, a->l);
check_r0_write(a->d);
tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
return true;
}
check_r0_write(rd);
switch (op0) {
case 0x00: /* l.slli */
LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6);
tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], S6);
break;
static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn)
{
LOG_DIS("l.srli r%d, r%d, %d\n", a->d, a->a, a->l);
check_r0_write(a->d);
tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
return true;
}
case 0x01: /* l.srli */
LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6);
tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], S6);
break;
static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn)
{
LOG_DIS("l.srai r%d, r%d, %d\n", a->d, a->a, a->l);
check_r0_write(a->d);
tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
return true;
}
case 0x02: /* l.srai */
LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6);
tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], S6);
break;
case 0x03: /* l.rori */
LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6);
tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], S6);
break;
default:
gen_illegal_exception(dc);
break;
}
static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn)
{
LOG_DIS("l.rori r%d, r%d, %d\n", a->d, a->a, a->l);
check_r0_write(a->d);
tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
return true;
}
static void dec_M(DisasContext *dc, uint32_t insn)
@ -1490,10 +1484,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
dec_M(dc, insn);
break;
case 0x2e:
dec_logic(dc, insn);
break;
case 0x2f:
dec_compi(dc, insn);
break;