target-ppc: Allow little-endian user mode.
This allows running PPC64 little-endian in user mode if target is configured that way. In PPC64 LE user mode we set MSR.LE during initialization. Signed-off-by: Doug Kwan <dougkwan@google.com> Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Doug Kwan
Alexander Graf
parent
d90b94cd78
commit
e22c357b3e
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@ -1484,7 +1484,7 @@ static int do_store_exclusive(CPUPPCState *env)
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{
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target_ulong addr;
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target_ulong page_addr;
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target_ulong val, val2 __attribute__((unused));
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target_ulong val, val2 __attribute__((unused)) = 0;
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int flags;
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int segv = 0;
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@ -1527,6 +1527,12 @@ static int do_store_exclusive(CPUPPCState *env)
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case 8: segv = put_user_u64(val, addr); break;
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case 16: {
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if (val2 == env->reserve_val2) {
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if (msr_le) {
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val2 = val;
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val = env->gpr[reg+1];
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} else {
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val2 = env->gpr[reg+1];
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}
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segv = put_user_u64(val, addr);
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if (!segv) {
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segv = put_user_u64(val2, addr + 8);
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@ -25,6 +25,15 @@
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//#define DEBUG_OP
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static inline bool needs_byteswap(const CPUPPCState *env)
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{
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#if defined(TARGET_WORDS_BIGENDIAN)
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return msr_le;
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#else
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return !msr_le;
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#endif
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}
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/*****************************************************************************/
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/* Memory load and stores */
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@ -44,7 +53,7 @@ static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
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void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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{
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for (; reg < 32; reg++) {
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if (msr_le) {
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if (needs_byteswap(env)) {
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env->gpr[reg] = bswap32(cpu_ldl_data(env, addr));
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} else {
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env->gpr[reg] = cpu_ldl_data(env, addr);
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@ -56,7 +65,7 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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{
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for (; reg < 32; reg++) {
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if (msr_le) {
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if (needs_byteswap(env)) {
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cpu_stl_data(env, addr, bswap32((uint32_t)env->gpr[reg]));
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} else {
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cpu_stl_data(env, addr, (uint32_t)env->gpr[reg]);
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@ -199,6 +208,11 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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#define LO_IDX 0
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#endif
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/* We use msr_le to determine index ordering in a vector. However,
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byteswapping is not simply controlled by msr_le. We also need to take
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into account endianness of the target. This is done for the little-endian
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PPC64 user-mode target. */
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#define LVE(name, access, swap, element) \
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void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
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target_ulong addr) \
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@ -207,9 +221,11 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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int adjust = HI_IDX*(n_elems - 1); \
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int sh = sizeof(r->element[0]) >> 1; \
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int index = (addr & 0xf) >> sh; \
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\
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if (msr_le) { \
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index = n_elems - index - 1; \
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} \
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\
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if (needs_byteswap(env)) { \
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r->element[LO_IDX ? index : (adjust - index)] = \
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swap(access(env, addr)); \
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} else { \
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@ -232,9 +248,11 @@ LVE(lvewx, cpu_ldl_data, bswap32, u32)
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int adjust = HI_IDX * (n_elems - 1); \
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int sh = sizeof(r->element[0]) >> 1; \
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int index = (addr & 0xf) >> sh; \
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\
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if (msr_le) { \
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index = n_elems - index - 1; \
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} \
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\
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if (needs_byteswap(env)) { \
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access(env, addr, swap(r->element[LO_IDX ? index : \
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(adjust - index)])); \
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} else { \
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@ -196,6 +196,7 @@ typedef struct DisasContext {
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int access_type;
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/* Translation flags */
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int le_mode;
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TCGMemOp default_tcg_memop_mask;
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#if defined(TARGET_PPC64)
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int sf_mode;
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int has_cfar;
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@ -210,6 +211,16 @@ typedef struct DisasContext {
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uint64_t insns_flags2;
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} DisasContext;
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/* Return true iff byteswap is needed in a scalar memop */
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static inline bool need_byteswap(const DisasContext *ctx)
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{
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#if defined(TARGET_WORDS_BIGENDIAN)
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return ctx->le_mode;
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#else
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return !ctx->le_mode;
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#endif
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}
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/* True when active word size < size of target_long. */
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#ifdef TARGET_PPC64
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# define NARROW_MODE(C) (!(C)->sf_mode)
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@ -2660,29 +2671,20 @@ static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
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static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
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if (unlikely(ctx->le_mode)) {
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tcg_gen_bswap16_tl(arg1, arg1);
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}
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TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
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tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
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}
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static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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if (unlikely(ctx->le_mode)) {
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tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
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tcg_gen_bswap16_tl(arg1, arg1);
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tcg_gen_ext16s_tl(arg1, arg1);
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} else {
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tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
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}
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TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
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tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
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}
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static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
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if (unlikely(ctx->le_mode)) {
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tcg_gen_bswap32_tl(arg1, arg1);
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}
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TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
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tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
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}
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static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
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@ -2695,12 +2697,8 @@ static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
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static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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if (unlikely(ctx->le_mode)) {
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tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
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tcg_gen_bswap32_tl(arg1, arg1);
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tcg_gen_ext32s_tl(arg1, arg1);
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} else
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tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
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TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
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tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
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}
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static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
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@ -2713,10 +2711,8 @@ static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
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static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
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{
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tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
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if (unlikely(ctx->le_mode)) {
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tcg_gen_bswap64_i64(arg1, arg1);
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}
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TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
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tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
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}
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static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
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@ -2726,28 +2722,14 @@ static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
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static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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if (unlikely(ctx->le_mode)) {
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TCGv t0 = tcg_temp_new();
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tcg_gen_ext16u_tl(t0, arg1);
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tcg_gen_bswap16_tl(t0, t0);
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tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
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tcg_temp_free(t0);
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} else {
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tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
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}
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TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
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tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
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}
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static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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if (unlikely(ctx->le_mode)) {
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TCGv t0 = tcg_temp_new();
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tcg_gen_ext32u_tl(t0, arg1);
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tcg_gen_bswap32_tl(t0, t0);
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tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
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tcg_temp_free(t0);
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} else {
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tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
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}
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TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
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tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
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}
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static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
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@ -2760,13 +2742,8 @@ static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
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static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
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{
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if (unlikely(ctx->le_mode)) {
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_bswap64_i64(t0, arg1);
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tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
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tcg_temp_free_i64(t0);
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} else
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tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
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TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
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tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
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}
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#define GEN_LD(name, ldop, opc, type) \
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@ -2910,6 +2887,8 @@ static void gen_lq(DisasContext *ctx)
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EA = tcg_temp_new();
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gen_addr_imm_index(ctx, EA, 0x0F);
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/* We only need to swap high and low halves. gen_qemu_ld64 does necessary
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64-bit byteswap already. */
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if (unlikely(ctx->le_mode)) {
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gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
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gen_addr_add(ctx, EA, EA, 8);
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@ -3028,6 +3007,8 @@ static void gen_std(DisasContext *ctx)
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EA = tcg_temp_new();
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gen_addr_imm_index(ctx, EA, 0x03);
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/* We only need to swap high and low halves. gen_qemu_st64 does
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necessary 64-bit byteswap already. */
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if (unlikely(ctx->le_mode)) {
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gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
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gen_addr_add(ctx, EA, EA, 8);
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@ -3057,23 +3038,20 @@ static void gen_std(DisasContext *ctx)
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}
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#endif
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/*** Integer load and store with byte reverse ***/
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/* lhbrx */
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static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
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if (likely(!ctx->le_mode)) {
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tcg_gen_bswap16_tl(arg1, arg1);
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}
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TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
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tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
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}
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GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
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/* lwbrx */
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static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
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if (likely(!ctx->le_mode)) {
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tcg_gen_bswap32_tl(arg1, arg1);
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}
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TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
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tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
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}
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GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
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@ -3081,10 +3059,8 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
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/* ldbrx */
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static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
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if (likely(!ctx->le_mode)) {
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tcg_gen_bswap64_tl(arg1, arg1);
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}
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TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
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tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
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}
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GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
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#endif /* TARGET_PPC64 */
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@ -3092,30 +3068,16 @@ GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
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/* sthbrx */
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static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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if (likely(!ctx->le_mode)) {
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TCGv t0 = tcg_temp_new();
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tcg_gen_ext16u_tl(t0, arg1);
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tcg_gen_bswap16_tl(t0, t0);
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tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
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tcg_temp_free(t0);
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} else {
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tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
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}
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TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
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tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
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}
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GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
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/* stwbrx */
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static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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if (likely(!ctx->le_mode)) {
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TCGv t0 = tcg_temp_new();
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tcg_gen_ext32u_tl(t0, arg1);
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tcg_gen_bswap32_tl(t0, t0);
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tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
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tcg_temp_free(t0);
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} else {
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tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
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}
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TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
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tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
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}
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GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
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@ -3123,14 +3085,8 @@ GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
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/* stdbrx */
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static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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if (likely(!ctx->le_mode)) {
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TCGv t0 = tcg_temp_new();
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tcg_gen_bswap64_tl(t0, arg1);
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tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
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tcg_temp_free(t0);
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} else {
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tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
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}
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TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
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tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
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}
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GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
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#endif /* TARGET_PPC64 */
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@ -3550,7 +3506,9 @@ static void gen_lfdp(DisasContext *ctx)
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}
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gen_set_access_type(ctx, ACCESS_FLOAT);
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EA = tcg_temp_new();
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gen_addr_imm_index(ctx, EA, 0); \
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gen_addr_imm_index(ctx, EA, 0);
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/* We only need to swap high and low halves. gen_qemu_ld64 does necessary
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64-bit byteswap already. */
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if (unlikely(ctx->le_mode)) {
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gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
||||
tcg_gen_addi_tl(EA, EA, 8);
|
||||
|
|
@ -3574,6 +3532,8 @@ static void gen_lfdpx(DisasContext *ctx)
|
|||
gen_set_access_type(ctx, ACCESS_FLOAT);
|
||||
EA = tcg_temp_new();
|
||||
gen_addr_reg_index(ctx, EA);
|
||||
/* We only need to swap high and low halves. gen_qemu_ld64 does necessary
|
||||
64-bit byteswap already. */
|
||||
if (unlikely(ctx->le_mode)) {
|
||||
gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
||||
tcg_gen_addi_tl(EA, EA, 8);
|
||||
|
|
@ -3722,7 +3682,9 @@ static void gen_stfdp(DisasContext *ctx)
|
|||
}
|
||||
gen_set_access_type(ctx, ACCESS_FLOAT);
|
||||
EA = tcg_temp_new();
|
||||
gen_addr_imm_index(ctx, EA, 0); \
|
||||
gen_addr_imm_index(ctx, EA, 0);
|
||||
/* We only need to swap high and low halves. gen_qemu_st64 does necessary
|
||||
64-bit byteswap already. */
|
||||
if (unlikely(ctx->le_mode)) {
|
||||
gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
||||
tcg_gen_addi_tl(EA, EA, 8);
|
||||
|
|
@ -3746,6 +3708,8 @@ static void gen_stfdpx(DisasContext *ctx)
|
|||
gen_set_access_type(ctx, ACCESS_FLOAT);
|
||||
EA = tcg_temp_new();
|
||||
gen_addr_reg_index(ctx, EA);
|
||||
/* We only need to swap high and low halves. gen_qemu_st64 does necessary
|
||||
64-bit byteswap already. */
|
||||
if (unlikely(ctx->le_mode)) {
|
||||
gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
||||
tcg_gen_addi_tl(EA, EA, 8);
|
||||
|
|
@ -6716,6 +6680,8 @@ static void glue(gen_, name)(DisasContext *ctx)
|
|||
EA = tcg_temp_new(); \
|
||||
gen_addr_reg_index(ctx, EA); \
|
||||
tcg_gen_andi_tl(EA, EA, ~0xf); \
|
||||
/* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
|
||||
64-bit byteswap already. */ \
|
||||
if (ctx->le_mode) { \
|
||||
gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
|
||||
tcg_gen_addi_tl(EA, EA, 8); \
|
||||
|
|
@ -6740,6 +6706,8 @@ static void gen_st##name(DisasContext *ctx) \
|
|||
EA = tcg_temp_new(); \
|
||||
gen_addr_reg_index(ctx, EA); \
|
||||
tcg_gen_andi_tl(EA, EA, ~0xf); \
|
||||
/* We only need to swap high and low halves. gen_qemu_st64 does necessary \
|
||||
64-bit byteswap already. */ \
|
||||
if (ctx->le_mode) { \
|
||||
gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
|
||||
tcg_gen_addi_tl(EA, EA, 8); \
|
||||
|
|
@ -11742,6 +11710,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
|
|||
ctx.insns_flags2 = env->insns_flags2;
|
||||
ctx.access_type = -1;
|
||||
ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
|
||||
ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
|
||||
#if defined(TARGET_PPC64)
|
||||
ctx.sf_mode = msr_is_64bit(env, env->msr);
|
||||
ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
|
||||
|
|
@ -11807,7 +11776,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
|
|||
ctx.nip, ctx.mem_idx, (int)msr_ir);
|
||||
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
|
||||
gen_io_start();
|
||||
if (unlikely(ctx.le_mode)) {
|
||||
if (unlikely(need_byteswap(&ctx))) {
|
||||
ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
|
||||
} else {
|
||||
ctx.opcode = cpu_ldl_code(env, ctx.nip);
|
||||
|
|
|
|||
|
|
@ -9315,6 +9315,9 @@ static void ppc_cpu_reset(CPUState *s)
|
|||
msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
|
||||
msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
|
||||
msr |= (target_ulong)1 << MSR_PR;
|
||||
#if !defined(TARGET_WORDS_BIGENDIAN)
|
||||
msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(TARGET_PPC64)
|
||||
|
|
|
|||
Loading…
Reference in a new issue