target/arm: Convert VFP round insns to decodetree
Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -2157,3 +2157,166 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
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tcg_temp_free_i32(tmp);
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return true;
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}
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static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
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{
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TCGv_ptr fpst;
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TCGv_i32 tmp;
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if (!dc_isar_feature(aa32_vrint, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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tmp = tcg_temp_new_i32();
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neon_load_reg32(tmp, a->vm);
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fpst = get_fpstatus_ptr(false);
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gen_helper_rints(tmp, tmp, fpst);
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neon_store_reg32(tmp, a->vd);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i32(tmp);
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return true;
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}
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static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_sp *a)
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{
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TCGv_ptr fpst;
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TCGv_i64 tmp;
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if (!dc_isar_feature(aa32_vrint, s)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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tmp = tcg_temp_new_i64();
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neon_load_reg64(tmp, a->vm);
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fpst = get_fpstatus_ptr(false);
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gen_helper_rintd(tmp, tmp, fpst);
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neon_store_reg64(tmp, a->vd);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i64(tmp);
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return true;
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}
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static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
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{
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TCGv_ptr fpst;
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TCGv_i32 tmp;
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TCGv_i32 tcg_rmode;
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if (!dc_isar_feature(aa32_vrint, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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tmp = tcg_temp_new_i32();
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neon_load_reg32(tmp, a->vm);
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fpst = get_fpstatus_ptr(false);
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tcg_rmode = tcg_const_i32(float_round_to_zero);
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
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gen_helper_rints(tmp, tmp, fpst);
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
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neon_store_reg32(tmp, a->vd);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i32(tcg_rmode);
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tcg_temp_free_i32(tmp);
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return true;
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}
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static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_sp *a)
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{
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TCGv_ptr fpst;
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TCGv_i64 tmp;
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TCGv_i32 tcg_rmode;
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if (!dc_isar_feature(aa32_vrint, s)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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tmp = tcg_temp_new_i64();
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neon_load_reg64(tmp, a->vm);
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fpst = get_fpstatus_ptr(false);
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tcg_rmode = tcg_const_i32(float_round_to_zero);
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
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gen_helper_rintd(tmp, tmp, fpst);
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
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neon_store_reg64(tmp, a->vd);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i64(tmp);
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tcg_temp_free_i32(tcg_rmode);
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return true;
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}
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static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a)
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{
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TCGv_ptr fpst;
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TCGv_i32 tmp;
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if (!dc_isar_feature(aa32_vrint, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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tmp = tcg_temp_new_i32();
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neon_load_reg32(tmp, a->vm);
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fpst = get_fpstatus_ptr(false);
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gen_helper_rints_exact(tmp, tmp, fpst);
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neon_store_reg32(tmp, a->vd);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i32(tmp);
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return true;
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}
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static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
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{
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TCGv_ptr fpst;
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TCGv_i64 tmp;
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if (!dc_isar_feature(aa32_vrint, s)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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tmp = tcg_temp_new_i64();
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neon_load_reg64(tmp, a->vm);
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fpst = get_fpstatus_ptr(false);
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gen_helper_rintd_exact(tmp, tmp, fpst);
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neon_store_reg64(tmp, a->vd);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i64(tmp);
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return true;
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}
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@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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return 1;
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case 15:
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switch (rn) {
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case 0 ... 11:
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case 0 ... 14:
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/* Already handled by decodetree */
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return 1;
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default:
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@ -3063,11 +3063,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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if (op == 15) {
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/* rn is opcode, encoded as per VFP_SREG_N. */
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switch (rn) {
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case 0x0c: /* vrintr */
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case 0x0d: /* vrintz */
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case 0x0e: /* vrintx */
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break;
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case 0x0f: /* vcvt double<->single */
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rd_is_dp = !dp;
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break;
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@ -3190,44 +3185,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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switch (op) {
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case 15: /* extension space */
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switch (rn) {
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case 12: /* vrintr */
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{
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TCGv_ptr fpst = get_fpstatus_ptr(0);
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if (dp) {
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gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
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} else {
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gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
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}
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tcg_temp_free_ptr(fpst);
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break;
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}
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case 13: /* vrintz */
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{
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TCGv_ptr fpst = get_fpstatus_ptr(0);
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TCGv_i32 tcg_rmode;
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tcg_rmode = tcg_const_i32(float_round_to_zero);
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
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if (dp) {
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gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
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} else {
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gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
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}
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
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tcg_temp_free_i32(tcg_rmode);
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tcg_temp_free_ptr(fpst);
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break;
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}
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case 14: /* vrintx */
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{
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TCGv_ptr fpst = get_fpstatus_ptr(0);
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if (dp) {
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gen_helper_rintd_exact(cpu_F0d, cpu_F0d, fpst);
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} else {
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gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpst);
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}
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tcg_temp_free_ptr(fpst);
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break;
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}
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case 15: /* single<->double conversion */
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if (dp) {
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gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
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@ -193,3 +193,18 @@ VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \
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vd=%vd_sp vm=%vm_dp
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VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... \
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vd=%vd_sp vm=%vm_sp
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VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... \
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vd=%vd_dp vm=%vm_dp
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VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... \
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vd=%vd_sp vm=%vm_sp
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VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... \
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vd=%vd_dp vm=%vm_dp
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VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \
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vd=%vd_sp vm=%vm_sp
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VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \
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vd=%vd_dp vm=%vm_dp
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