haraldwolff/qemu-patch-raspberry4
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

target/mips: Alias MSA vector registers on FPU scalar registers

Browse source 
Commits 863f264d10 ("add msa_reset(), global msa register") and
cb269f273f ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.

It is not very clear to have FPU registers displayed with MSA
register names, even if MSA ASE is not present.

Instead of aliasing FPU registers to the MSA ones (even when MSA
is absent), we now alias the MSA ones to the FPU ones (only when
MSA is present).

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-7-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-11-29 21:11:00 +01:00
parent 7e2a619a04
commit e2665f314d
1 changed files with 10 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
target/mips/translate.c
View file

@ -31562,16 +31562,20 @@ void mips_tcg_init(void)
offsetof(CPUMIPSState,
active_tc.gpr[i]),
regnames[i]);
for (i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
msa_wr_d[i * 2] =
tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]);
fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
}
/* MSA */
for (i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
/*
* The scalar floating-point unit (FPU) registers are mapped on
* the MSA vector registers.
* The MSA vector registers are mapped on the
* scalar floating-point unit (FPU) registers.
*/
fpu_f64[i] = msa_wr_d[i * 2];
msa_wr_d[i * 2] = fpu_f64[i];
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);