arm/highbank.c: Fix MPCore periphbase name
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the code that this is the base address of the MPCore. Rename to MPCORE_PERIPHBASE accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 90798bd3507205c16238b8b19a1a58c5437cf7ca.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -28,11 +28,11 @@
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#include "exec/address-spaces.h"
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#include "exec/address-spaces.h"
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#include "qemu/error-report.h"
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#include "qemu/error-report.h"
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#define SMP_BOOT_ADDR 0x100
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#define SMP_BOOT_ADDR 0x100
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#define SMP_BOOT_REG 0x40
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#define SMP_BOOT_REG 0x40
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#define GIC_BASE_ADDR 0xfff10000
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#define MPCORE_PERIPHBASE 0xfff10000
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#define NIRQ_GIC 160
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#define NIRQ_GIC 160
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/* Board init. */
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/* Board init. */
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@ -55,7 +55,7 @@ static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
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0xe1110001, /* tst r1, r1 */
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0xe1110001, /* tst r1, r1 */
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0x0afffffb, /* beq <wfi> */
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0x0afffffb, /* beq <wfi> */
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0xe12fff11, /* bx r1 */
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0xe12fff11, /* bx r1 */
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GIC_BASE_ADDR /* privbase: gic address. */
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MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */
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};
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};
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for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
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for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
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smpboot[n] = tswap32(smpboot[n]);
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smpboot[n] = tswap32(smpboot[n]);
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@ -236,7 +236,8 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
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cpu = ARM_CPU(object_new(object_class_get_name(oc)));
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cpu = ARM_CPU(object_new(object_class_get_name(oc)));
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object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err);
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object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
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&err);
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if (err) {
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if (err) {
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error_report("%s", error_get_pretty(err));
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error_report("%s", error_get_pretty(err));
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exit(1);
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exit(1);
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@ -287,7 +288,7 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
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qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
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qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
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qdev_init_nofail(dev);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
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sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
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for (n = 0; n < smp_cpus; n++) {
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for (n = 0; n < smp_cpus; n++) {
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sysbus_connect_irq(busdev, n, cpu_irq[n]);
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sysbus_connect_irq(busdev, n, cpu_irq[n]);
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}
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}
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