hw/dma/xilinx_axidma: Add DMA memory-region property
Add DMA memory-region property to externally control what address-space this DMA operates on. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200506082513.18751-5-edgar.iglesias@gmail.com>
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@ -33,6 +33,7 @@
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#include "qemu/log.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/module.h"
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#include "sysemu/dma.h"
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#include "hw/stream.h"
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#include "hw/stream.h"
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#define D(x)
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#define D(x)
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@ -103,6 +104,7 @@ enum {
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};
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};
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struct Stream {
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struct Stream {
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struct XilinxAXIDMA *dma;
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ptimer_state *ptimer;
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ptimer_state *ptimer;
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qemu_irq irq;
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qemu_irq irq;
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@ -125,6 +127,9 @@ struct XilinxAXIDMAStreamSlave {
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struct XilinxAXIDMA {
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struct XilinxAXIDMA {
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SysBusDevice busdev;
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SysBusDevice busdev;
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MemoryRegion iomem;
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MemoryRegion iomem;
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MemoryRegion *dma_mr;
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AddressSpace as;
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uint32_t freqhz;
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uint32_t freqhz;
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StreamSlave *tx_data_dev;
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StreamSlave *tx_data_dev;
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StreamSlave *tx_control_dev;
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StreamSlave *tx_control_dev;
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@ -186,7 +191,7 @@ static void stream_desc_load(struct Stream *s, hwaddr addr)
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{
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{
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struct SDesc *d = &s->desc;
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struct SDesc *d = &s->desc;
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cpu_physical_memory_read(addr, d, sizeof *d);
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address_space_read(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, d, sizeof *d);
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/* Convert from LE into host endianness. */
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/* Convert from LE into host endianness. */
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d->buffer_address = le64_to_cpu(d->buffer_address);
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d->buffer_address = le64_to_cpu(d->buffer_address);
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@ -204,7 +209,8 @@ static void stream_desc_store(struct Stream *s, hwaddr addr)
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d->nxtdesc = cpu_to_le64(d->nxtdesc);
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d->nxtdesc = cpu_to_le64(d->nxtdesc);
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d->control = cpu_to_le32(d->control);
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d->control = cpu_to_le32(d->control);
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d->status = cpu_to_le32(d->status);
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d->status = cpu_to_le32(d->status);
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cpu_physical_memory_write(addr, d, sizeof *d);
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address_space_write(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED,
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d, sizeof *d);
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}
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}
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static void stream_update_irq(struct Stream *s)
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static void stream_update_irq(struct Stream *s)
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@ -286,8 +292,9 @@ static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev,
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txlen + s->pos);
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txlen + s->pos);
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}
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}
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cpu_physical_memory_read(s->desc.buffer_address,
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address_space_read(&s->dma->as, s->desc.buffer_address,
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s->txbuf + s->pos, txlen);
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MEMTXATTRS_UNSPECIFIED,
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s->txbuf + s->pos, txlen);
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s->pos += txlen;
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s->pos += txlen;
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if (stream_desc_eof(&s->desc)) {
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if (stream_desc_eof(&s->desc)) {
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@ -336,7 +343,8 @@ static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
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rxlen = len;
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rxlen = len;
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}
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}
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cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen);
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address_space_write(&s->dma->as, s->desc.buffer_address,
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MEMTXATTRS_UNSPECIFIED, buf + pos, rxlen);
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len -= rxlen;
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len -= rxlen;
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pos += rxlen;
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pos += rxlen;
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@ -525,6 +533,7 @@ static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
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XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
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XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
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&s->rx_control_dev);
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&s->rx_control_dev);
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Error *local_err = NULL;
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Error *local_err = NULL;
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int i;
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object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA,
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object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA,
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(Object **)&ds->dma,
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(Object **)&ds->dma,
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@ -545,17 +554,19 @@ static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
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goto xilinx_axidma_realize_fail;
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goto xilinx_axidma_realize_fail;
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}
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}
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int i;
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for (i = 0; i < 2; i++) {
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for (i = 0; i < 2; i++) {
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struct Stream *st = &s->streams[i];
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struct Stream *st = &s->streams[i];
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st->dma = s;
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st->nr = i;
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st->nr = i;
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st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT);
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st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT);
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ptimer_transaction_begin(st->ptimer);
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ptimer_transaction_begin(st->ptimer);
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ptimer_set_freq(st->ptimer, s->freqhz);
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ptimer_set_freq(st->ptimer, s->freqhz);
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ptimer_transaction_commit(st->ptimer);
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ptimer_transaction_commit(st->ptimer);
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}
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}
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address_space_init(&s->as,
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s->dma_mr ? s->dma_mr : get_system_memory(), "dma");
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return;
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return;
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xilinx_axidma_realize_fail:
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xilinx_axidma_realize_fail:
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@ -575,6 +586,11 @@ static void xilinx_axidma_init(Object *obj)
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&s->rx_control_dev, sizeof(s->rx_control_dev),
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&s->rx_control_dev, sizeof(s->rx_control_dev),
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TYPE_XILINX_AXI_DMA_CONTROL_STREAM, &error_abort,
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TYPE_XILINX_AXI_DMA_CONTROL_STREAM, &error_abort,
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NULL);
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NULL);
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object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
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(Object **)&s->dma_mr,
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qdev_prop_allow_set_link_before_realize,
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OBJ_PROP_LINK_STRONG,
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&error_abort);
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sysbus_init_irq(sbd, &s->streams[0].irq);
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sysbus_init_irq(sbd, &s->streams[0].irq);
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sysbus_init_irq(sbd, &s->streams[1].irq);
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sysbus_init_irq(sbd, &s->streams[1].irq);
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