target-arm: Add ARMCPU fields for GIC CPU i/f config
Add fields to the ARMCPU structure to allow CPU classes to specify the configurable aspects of their GIC CPU interface. In particular, the virtualization support allows different values for number of list registers, priority bits and preemption bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1483977924-14522-6-git-send-email-peter.maydell@linaro.org
This commit is contained in:
parent
5454006a7c
commit
e45868a3f3
|
@ -662,6 +662,11 @@ struct ARMCPU {
|
|||
uint32_t dcz_blocksize;
|
||||
uint64_t rvbar;
|
||||
|
||||
/* Configurable aspects of GIC cpu interface (which is part of the CPU) */
|
||||
int gic_num_lrs; /* number of list registers */
|
||||
int gic_vpribits; /* number of virtual priority bits */
|
||||
int gic_vprebits; /* number of virtual preemption bits */
|
||||
|
||||
ARMELChangeHook *el_change_hook;
|
||||
void *el_change_hook_opaque;
|
||||
};
|
||||
|
|
|
@ -147,6 +147,9 @@ static void aarch64_a57_initfn(Object *obj)
|
|||
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
|
||||
cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
|
||||
cpu->dcz_blocksize = 4; /* 64 bytes */
|
||||
cpu->gic_num_lrs = 4;
|
||||
cpu->gic_vpribits = 5;
|
||||
cpu->gic_vprebits = 5;
|
||||
define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
|
||||
}
|
||||
|
||||
|
@ -201,6 +204,9 @@ static void aarch64_a53_initfn(Object *obj)
|
|||
cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
|
||||
cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
|
||||
cpu->dcz_blocksize = 4; /* 64 bytes */
|
||||
cpu->gic_num_lrs = 4;
|
||||
cpu->gic_vpribits = 5;
|
||||
cpu->gic_vprebits = 5;
|
||||
define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in a new issue