tcg/optimize: fix known-zero bits for right shift ops
32-bit versions of sar and shr ops should not propagate known-zero bits from the unused 32 high bits. For sar it could even lead to wrong code being generated. Cc: qemu-stable@nongnu.org Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -726,16 +726,25 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr,
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mask = temps[args[1]].mask & mask;
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mask = temps[args[1]].mask & mask;
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break;
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break;
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CASE_OP_32_64(sar):
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case INDEX_op_sar_i32:
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if (temps[args[2]].state == TCG_TEMP_CONST) {
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if (temps[args[2]].state == TCG_TEMP_CONST) {
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mask = ((tcg_target_long)temps[args[1]].mask
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mask = (int32_t)temps[args[1]].mask >> temps[args[2]].val;
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>> temps[args[2]].val);
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}
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break;
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case INDEX_op_sar_i64:
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if (temps[args[2]].state == TCG_TEMP_CONST) {
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mask = (int64_t)temps[args[1]].mask >> temps[args[2]].val;
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}
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}
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break;
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break;
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CASE_OP_32_64(shr):
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case INDEX_op_shr_i32:
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if (temps[args[2]].state == TCG_TEMP_CONST) {
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if (temps[args[2]].state == TCG_TEMP_CONST) {
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mask = temps[args[1]].mask >> temps[args[2]].val;
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mask = (uint32_t)temps[args[1]].mask >> temps[args[2]].val;
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}
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break;
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case INDEX_op_shr_i64:
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if (temps[args[2]].state == TCG_TEMP_CONST) {
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mask = (uint64_t)temps[args[1]].mask >> temps[args[2]].val;
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}
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}
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break;
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break;
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