intel_iommu: TM field should not be in reserved bits
When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi <qi1.zhang@intel.com> Signed-off-by: Qi, Yadong <yadong.qi@intel.com> Message-Id: <20191125003321.5669-3-yadong.qi@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -3554,13 +3554,16 @@ static void vtd_init(IntelIOMMUState *s)
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* Rsvd field masks for spte
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* Rsvd field masks for spte
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*/
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*/
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vtd_spte_rsvd[0] = ~0ULL;
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vtd_spte_rsvd[0] = ~0ULL;
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vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
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x86_iommu->dt_supported);
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vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
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vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
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x86_iommu->dt_supported);
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vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
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x86_iommu->dt_supported);
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if (x86_iommu_ir_supported(x86_iommu)) {
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if (x86_iommu_ir_supported(x86_iommu)) {
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s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
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s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
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@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc;
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#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
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#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
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/* Rsvd field masks for spte */
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/* Rsvd field masks for spte */
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#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
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#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
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dt_supported ? \
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(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
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(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
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#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
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(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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@ -396,9 +398,13 @@ typedef union VTDInvDesc VTDInvDesc;
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#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
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#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
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(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
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#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
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dt_supported ? \
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(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
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(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
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#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
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dt_supported ? \
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(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
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(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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/* Information about page-selective IOTLB invalidate */
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/* Information about page-selective IOTLB invalidate */
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@ -503,5 +509,6 @@ typedef struct VTDRootEntry VTDRootEntry;
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#define VTD_SL_W (1ULL << 1)
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#define VTD_SL_W (1ULL << 1)
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#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
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#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
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#define VTD_SL_IGN_COM 0xbff0000000000000ULL
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#define VTD_SL_IGN_COM 0xbff0000000000000ULL
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#define VTD_SL_TM (1ULL << 62)
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#endif
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#endif
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