target/s390x: Implement the MVPG condition-code-option bit
If the CCO bit is set, MVPG should not generate an exception but report page translation faults via a CC code. Create a new helper, access_prepare_nf, which can use probe_access_flags in non-faulting mode, and then handle watchpoints. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [thuth: Added logic to still inject protection exceptions] Signed-off-by: Thomas Huth <thuth@redhat.com> [david: Look at env->tlb_fill_exc to determine if there was an exception] Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210315085449.34676-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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@ -114,6 +114,11 @@ struct CPUS390XState {
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uint64_t diag318_info;
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#if !defined(CONFIG_USER_ONLY)
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uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */
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int tlb_fill_exc; /* exception number seen during tlb_fill */
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#endif
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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@ -164,6 +164,9 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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tec = 0; /* unused */
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}
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env->tlb_fill_exc = excp;
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env->tlb_fill_tec = tec;
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if (!excp) {
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qemu_log_mask(CPU_LOG_MMU,
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"%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n",
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@ -130,28 +130,103 @@ typedef struct S390Access {
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int mmu_idx;
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} S390Access;
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/*
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* With nonfault=1, return the PGM_ exception that would have been injected
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* into the guest; return 0 if no exception was detected.
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*
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* For !CONFIG_USER_ONLY, the TEC is stored stored to env->tlb_fill_tec.
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* For CONFIG_USER_ONLY, the faulting address is stored to env->__excp_addr.
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*/
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static int s390_probe_access(CPUArchState *env, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx,
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bool nonfault, void **phost, uintptr_t ra)
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{
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int flags;
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#if defined(CONFIG_USER_ONLY)
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flags = page_get_flags(addr);
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if (!(flags & (access_type == MMU_DATA_LOAD ? PAGE_READ : PAGE_WRITE))) {
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env->__excp_addr = addr;
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flags = (flags & PAGE_VALID) ? PGM_PROTECTION : PGM_ADDRESSING;
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if (nonfault) {
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return flags;
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}
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tcg_s390_program_interrupt(env, flags, ra);
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}
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*phost = g2h(env_cpu(env), addr);
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#else
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/*
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* For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL
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* to detect if there was an exception during tlb_fill().
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*/
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env->tlb_fill_exc = 0;
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flags = probe_access_flags(env, addr, access_type, mmu_idx, nonfault, phost,
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ra);
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if (env->tlb_fill_exc) {
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return env->tlb_fill_exc;
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}
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if (unlikely(flags & TLB_WATCHPOINT)) {
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/* S390 does not presently use transaction attributes. */
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cpu_check_watchpoint(env_cpu(env), addr, size,
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MEMTXATTRS_UNSPECIFIED,
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(access_type == MMU_DATA_STORE
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? BP_MEM_WRITE : BP_MEM_READ), ra);
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}
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#endif
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return 0;
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}
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static int access_prepare_nf(S390Access *access, CPUS390XState *env,
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bool nonfault, vaddr vaddr1, int size,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t ra)
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{
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void *haddr1, *haddr2 = NULL;
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int size1, size2, exc;
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vaddr vaddr2 = 0;
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assert(size > 0 && size <= 4096);
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size1 = MIN(size, -(vaddr1 | TARGET_PAGE_MASK)),
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size2 = size - size1;
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exc = s390_probe_access(env, vaddr1, size1, access_type, mmu_idx, nonfault,
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&haddr1, ra);
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if (exc) {
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return exc;
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}
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if (unlikely(size2)) {
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/* The access crosses page boundaries. */
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vaddr2 = wrap_address(env, vaddr1 + size1);
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exc = s390_probe_access(env, vaddr2, size2, access_type, mmu_idx,
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nonfault, &haddr2, ra);
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if (exc) {
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return exc;
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}
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}
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*access = (S390Access) {
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.vaddr1 = vaddr1,
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.vaddr2 = vaddr2,
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.haddr1 = haddr1,
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.haddr2 = haddr2,
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.size1 = size1,
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.size2 = size2,
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.mmu_idx = mmu_idx
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};
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return 0;
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}
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static S390Access access_prepare(CPUS390XState *env, vaddr vaddr, int size,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t ra)
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{
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S390Access access = {
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.vaddr1 = vaddr,
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.size1 = MIN(size, -(vaddr | TARGET_PAGE_MASK)),
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.mmu_idx = mmu_idx,
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};
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g_assert(size > 0 && size <= 4096);
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access.haddr1 = probe_access(env, access.vaddr1, access.size1, access_type,
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mmu_idx, ra);
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if (unlikely(access.size1 != size)) {
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/* The access crosses page boundaries. */
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access.vaddr2 = wrap_address(env, vaddr + access.size1);
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access.size2 = size - access.size1;
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access.haddr2 = probe_access(env, access.vaddr2, access.size2,
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access_type, mmu_idx, ra);
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}
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return access;
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S390Access ret;
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int exc = access_prepare_nf(&ret, env, false, vaddr, size,
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access_type, mmu_idx, ra);
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assert(!exc);
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return ret;
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}
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/* Helper to handle memset on a single page. */
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@ -845,8 +920,10 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, uint64_t r1, uint64_t r2)
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const int mmu_idx = cpu_mmu_index(env, false);
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const bool f = extract64(r0, 11, 1);
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const bool s = extract64(r0, 10, 1);
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const bool cco = extract64(r0, 8, 1);
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uintptr_t ra = GETPC();
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S390Access srca, desta;
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int exc;
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if ((f && s) || extract64(r0, 12, 4)) {
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tcg_s390_program_interrupt(env, PGM_SPECIFICATION, GETPC());
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@ -858,13 +935,26 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, uint64_t r1, uint64_t r2)
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/*
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* TODO:
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* - Access key handling
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* - CC-option with surpression of page-translation exceptions
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* - Store r1/r2 register identifiers at real location 162
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*/
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srca = access_prepare(env, r2, TARGET_PAGE_SIZE, MMU_DATA_LOAD, mmu_idx,
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ra);
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desta = access_prepare(env, r1, TARGET_PAGE_SIZE, MMU_DATA_STORE, mmu_idx,
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ra);
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exc = access_prepare_nf(&srca, env, cco, r2, TARGET_PAGE_SIZE,
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MMU_DATA_LOAD, mmu_idx, ra);
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if (exc) {
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return 2;
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}
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exc = access_prepare_nf(&desta, env, cco, r1, TARGET_PAGE_SIZE,
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MMU_DATA_STORE, mmu_idx, ra);
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if (exc) {
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if (exc == PGM_PROTECTION) {
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#if !defined(CONFIG_USER_ONLY)
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stq_phys(env_cpu(env)->as,
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env->psa + offsetof(LowCore, trans_exc_code),
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env->tlb_fill_tec);
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#endif
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tcg_s390_program_interrupt(env, PGM_PROTECTION, ra);
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}
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return 1;
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}
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access_memmove(env, &desta, &srca, ra);
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return 0; /* data moved */
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}
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