target-sparc: simplify ultrasparc_tsb_pointer
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
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15f746cedc
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e5673ee45e
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@ -70,44 +70,35 @@
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#define QT1 (env->qt1)
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#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
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static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env, uint64_t tsb,
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uint64_t *tsb_ptr,
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uint64_t tag_access_register,
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int idx, uint64_t *cfg_ptr)
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/* Calculates TSB pointer value for fault page size
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* UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers
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* UA2005 holds the page size configuration in mmu_ctx registers */
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static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env,
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const SparcV9MMU *mmu, const int idx)
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{
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uint64_t tsb_register;
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int page_size;
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if (cpu_has_hypervisor(env)) {
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int tsb_index = 0;
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int ctx = tag_access_register & 0x1fffULL;
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uint64_t ctx_register = cfg_ptr[ctx ? 1 : 0];
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int ctx = mmu->tag_access & 0x1fffULL;
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uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0];
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tsb_index = idx;
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tsb_index |= ctx ? 2 : 0;
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page_size = idx ? ctx_register >> 8 : ctx_register;
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page_size &= 7;
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tsb_register = tsb_ptr[tsb_index];
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tsb_register = mmu->sun4v_tsb_pointers[tsb_index];
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} else {
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page_size = idx;
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tsb_register = tsb;
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tsb_register = mmu->tsb;
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}
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uint64_t tsb_base = tsb_register & ~0x1fffULL;
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int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
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int tsb_size = tsb_register & 0xf;
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/* discard lower 13 bits which hold tag access context */
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uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
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uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size;
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/* now reorder bits */
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uint64_t tsb_base_mask = ~0x1fffULL;
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uint64_t va = tag_access_va;
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/* move va bits to correct position */
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va >>= 3 * page_size + 9;
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tsb_base_mask <<= tsb_size;
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/* move va bits to correct position,
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* the context bits will be masked out later */
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uint64_t va = mmu->tag_access >> (3 * page_size + 9);
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/* calculate tsb_base mask and adjust va if split is in use */
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if (tsb_split) {
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@ -119,7 +110,7 @@ static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env, uint64_t tsb,
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tsb_base_mask <<= 1;
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}
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return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
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return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
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}
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/* Calculates tag target register value by reordering bits
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@ -1268,20 +1259,14 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
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{
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/* env->immuregs[5] holds I-MMU TSB register value
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env->immuregs[6] holds I-MMU Tag Access register value */
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ret = ultrasparc_tsb_pointer(env, env->immu.tsb,
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env->immu.sun4v_tsb_pointers,
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env->immu.tag_access,
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0, env->immu.sun4v_ctx_config);
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ret = ultrasparc_tsb_pointer(env, &env->immu, 0);
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break;
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}
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case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */
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{
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/* env->immuregs[5] holds I-MMU TSB register value
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env->immuregs[6] holds I-MMU Tag Access register value */
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ret = ultrasparc_tsb_pointer(env, env->immu.tsb,
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env->immu.sun4v_tsb_pointers,
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env->immu.tag_access,
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1, env->immu.sun4v_ctx_config);
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ret = ultrasparc_tsb_pointer(env, &env->immu, 1);
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break;
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}
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case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
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@ -1340,20 +1325,14 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
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{
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/* env->dmmuregs[5] holds D-MMU TSB register value
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env->dmmuregs[6] holds D-MMU Tag Access register value */
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ret = ultrasparc_tsb_pointer(env, env->dmmu.tsb,
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env->dmmu.sun4v_tsb_pointers,
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env->dmmu.tag_access,
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0, env->dmmu.sun4v_ctx_config);
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ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0);
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break;
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}
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case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */
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{
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/* env->dmmuregs[5] holds D-MMU TSB register value
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env->dmmuregs[6] holds D-MMU Tag Access register value */
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ret = ultrasparc_tsb_pointer(env, env->dmmu.tsb,
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env->dmmu.sun4v_tsb_pointers,
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env->dmmu.tag_access,
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1, env->dmmu.sun4v_ctx_config);
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ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1);
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break;
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}
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case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
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