more generic serial port (initial patch by Jocelyn Mayer)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1654 c046a42c-6fe2-441c-8c8c-71466251a162
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2023a2c836
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@ -251,7 +251,7 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
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isa_pic = pic_init(pic_irq_request, env);
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isa_pic = pic_init(pic_irq_request, env);
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pit = pit_init(0x40, 0);
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pit = pit_init(0x40, 0);
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serial_init(0x3f8, 4, serial_hds[0]);
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serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
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vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,
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vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,
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vga_ram_size, 0, 0);
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vga_ram_size, 0, 0);
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5
hw/pc.c
5
hw/pc.c
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@ -599,7 +599,7 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
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/* XXX: enable it in all cases */
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/* XXX: enable it in all cases */
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env->cpuid_features |= CPUID_APIC;
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env->cpuid_features |= CPUID_APIC;
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}
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}
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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qemu_register_reset(main_cpu_reset, env);
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if (pci_enabled) {
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if (pci_enabled) {
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apic_init(env);
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apic_init(env);
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@ -757,7 +757,8 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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if (serial_hds[i]) {
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if (serial_hds[i]) {
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serial_init(serial_io[i], serial_irq[i], serial_hds[i]);
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serial_init(&pic_set_irq_new, isa_pic,
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serial_io[i], serial_irq[i], serial_hds[i]);
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}
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}
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}
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}
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@ -433,7 +433,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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isa_pic = pic_init(pic_irq_request, NULL);
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isa_pic = pic_init(pic_irq_request, NULL);
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/* XXX: use Mac Serial port */
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, 4, serial_hds[0]);
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serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
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for(i = 0; i < nb_nics; i++) {
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for(i = 0; i < nb_nics; i++) {
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pci_ne2000_init(pci_bus, &nd_table[i]);
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pci_ne2000_init(pci_bus, &nd_table[i]);
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@ -482,7 +482,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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isa_pic = pic_init(pic_irq_request, NULL);
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isa_pic = pic_init(pic_irq_request, NULL);
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/* XXX: use Mac Serial port */
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, 4, serial_hds[0]);
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serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
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for(i = 0; i < nb_nics; i++) {
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for(i = 0; i < nb_nics; i++) {
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pci_ne2000_init(pci_bus, &nd_table[i]);
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pci_ne2000_init(pci_bus, &nd_table[i]);
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@ -525,6 +525,7 @@ static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
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{
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{
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CPUState *env;
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CPUState *env;
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char buf[1024];
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char buf[1024];
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SetIRQFunc *set_irq;
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m48t59_t *nvram;
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m48t59_t *nvram;
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int PPC_io_memory;
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int PPC_io_memory;
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int linux_boot, i, nb_nics1, bios_size;
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int linux_boot, i, nb_nics1, bios_size;
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@ -618,7 +619,7 @@ static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
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isa_pic = pic_init(pic_irq_request, first_cpu);
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isa_pic = pic_init(pic_irq_request, first_cpu);
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// pit = pit_init(0x40, 0);
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// pit = pit_init(0x40, 0);
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serial_init(0x3f8, 4, serial_hds[0]);
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serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
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nb_nics1 = nb_nics;
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nb_nics1 = nb_nics;
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if (nb_nics1 > NE2000_NB_MAX)
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if (nb_nics1 > NE2000_NB_MAX)
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nb_nics1 = NE2000_NB_MAX;
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nb_nics1 = NE2000_NB_MAX;
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100
hw/serial.c
100
hw/serial.c
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@ -83,9 +83,13 @@ struct SerialState {
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/* NOTE: this hidden state is necessary for tx irq generation as
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/* NOTE: this hidden state is necessary for tx irq generation as
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it can be reset while reading iir */
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it can be reset while reading iir */
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int thr_ipending;
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int thr_ipending;
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SetIRQFunc *set_irq;
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void *irq_opaque;
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int irq;
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int irq;
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CharDriverState *chr;
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CharDriverState *chr;
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int last_break_enable;
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int last_break_enable;
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target_ulong base;
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int it_shift;
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};
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};
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static void serial_update_irq(SerialState *s)
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static void serial_update_irq(SerialState *s)
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@ -98,9 +102,9 @@ static void serial_update_irq(SerialState *s)
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s->iir = UART_IIR_NO_INT;
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s->iir = UART_IIR_NO_INT;
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}
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}
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if (s->iir != UART_IIR_NO_INT) {
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if (s->iir != UART_IIR_NO_INT) {
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pic_set_irq(s->irq, 1);
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s->set_irq(s->irq_opaque, s->irq, 1);
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} else {
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} else {
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pic_set_irq(s->irq, 0);
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s->set_irq(s->irq_opaque, s->irq, 0);
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}
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}
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}
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}
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@ -339,13 +343,16 @@ static int serial_load(QEMUFile *f, void *opaque, int version_id)
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}
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}
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/* If fd is zero, it means that the serial device uses the console */
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/* If fd is zero, it means that the serial device uses the console */
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SerialState *serial_init(int base, int irq, CharDriverState *chr)
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SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
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int base, int irq, CharDriverState *chr)
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{
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{
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SerialState *s;
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SerialState *s;
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s = qemu_mallocz(sizeof(SerialState));
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s = qemu_mallocz(sizeof(SerialState));
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if (!s)
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if (!s)
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return NULL;
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return NULL;
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s->set_irq = set_irq;
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s->irq_opaque = opaque;
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s->irq = irq;
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s->irq = irq;
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s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
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s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
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s->iir = UART_IIR_NO_INT;
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s->iir = UART_IIR_NO_INT;
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@ -359,3 +366,90 @@ SerialState *serial_init(int base, int irq, CharDriverState *chr)
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qemu_chr_add_event_handler(chr, serial_event);
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qemu_chr_add_event_handler(chr, serial_event);
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return s;
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return s;
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}
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}
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/* Memory mapped interface */
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static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
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{
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SerialState *s = opaque;
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return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
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}
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static void serial_mm_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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SerialState *s = opaque;
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serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
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}
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static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
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{
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SerialState *s = opaque;
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return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
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}
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static void serial_mm_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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SerialState *s = opaque;
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serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
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}
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static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
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{
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SerialState *s = opaque;
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return serial_ioport_read(s, (addr - s->base) >> s->it_shift);
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}
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static void serial_mm_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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SerialState *s = opaque;
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serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
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}
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static CPUReadMemoryFunc *serial_mm_read[] = {
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&serial_mm_readb,
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&serial_mm_readw,
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&serial_mm_readl,
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};
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static CPUWriteMemoryFunc *serial_mm_write[] = {
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&serial_mm_writeb,
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&serial_mm_writew,
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&serial_mm_writel,
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};
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SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
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target_ulong base, int it_shift,
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int irq, CharDriverState *chr)
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{
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SerialState *s;
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int s_io_memory;
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s = qemu_mallocz(sizeof(SerialState));
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if (!s)
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return NULL;
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s->set_irq = set_irq;
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s->irq_opaque = opaque;
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s->irq = irq;
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s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
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s->iir = UART_IIR_NO_INT;
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s->base = base;
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s->it_shift = it_shift;
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register_savevm("serial", base, 1, serial_save, serial_load, s);
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s_io_memory = cpu_register_io_memory(0, serial_mm_read,
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serial_mm_write, s);
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cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
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s->chr = chr;
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qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s);
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qemu_chr_add_event_handler(chr, serial_event);
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return s;
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}
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@ -335,7 +335,8 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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if (serial_hds[i]) {
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if (serial_hds[i]) {
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serial_init(serial_io[i], serial_irq[i], serial_hds[i]);
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serial_init(&pic_set_irq_new, NULL,
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serial_io[i], serial_irq[i], serial_hds[i]);
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}
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}
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}
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}
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6
vl.h
6
vl.h
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@ -733,7 +733,11 @@ void rtc_set_date(RTCState *s, const struct tm *tm);
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/* serial.c */
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/* serial.c */
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typedef struct SerialState SerialState;
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typedef struct SerialState SerialState;
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SerialState *serial_init(int base, int irq, CharDriverState *chr);
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SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
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int base, int irq, CharDriverState *chr);
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SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
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target_ulong base, int it_shift,
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int irq, CharDriverState *chr);
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/* parallel.c */
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/* parallel.c */
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