tcg/aarch64: limit mul_vec size
In AdvSIMD we can only do 32x32 integer multiples although SVE is capable of larger 64 bit multiples. As a result we can end up generating invalid opcodes. Fix this by only reprting we can emit mul vector ops if the size is small enough. Fixes a crash on: sve-all-short-v8.3+sve@vq3/insn_mul_z_zi___INC.risu.bin When running on AArch64 hardware. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20180719154248.29669-1-alex.bennee@linaro.org> [rth: Removed the tcg_debug_assert -- there are plenty of other cases that we do not diagnose within the insn encoding helpers.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -2219,7 +2219,6 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
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switch (opc) {
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switch (opc) {
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case INDEX_op_add_vec:
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case INDEX_op_add_vec:
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case INDEX_op_sub_vec:
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case INDEX_op_sub_vec:
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case INDEX_op_mul_vec:
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case INDEX_op_and_vec:
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case INDEX_op_and_vec:
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case INDEX_op_or_vec:
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case INDEX_op_or_vec:
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case INDEX_op_xor_vec:
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case INDEX_op_xor_vec:
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@ -2232,6 +2231,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
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case INDEX_op_shri_vec:
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case INDEX_op_shri_vec:
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case INDEX_op_sari_vec:
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case INDEX_op_sari_vec:
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return 1;
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return 1;
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case INDEX_op_mul_vec:
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return vece < MO_64;
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default:
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default:
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return 0;
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return 0;
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