target-or32: Add target stubs and QOM cpu
Add OpenRISC target stubs, QOM cpu and basic machine. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>stable-1.2
Jia Liu
Blue Swirl
parent
a21143486b
commit
e67db06e9f
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@ -79,6 +79,8 @@ int graphic_depth = 15;
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#define QEMU_ARCH QEMU_ARCH_MICROBLAZE
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#elif defined(TARGET_MIPS)
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#define QEMU_ARCH QEMU_ARCH_MIPS
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#elif defined(TARGET_OPENRISC)
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#define QEMU_ARCH QEMU_ARCH_OPENRISC
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#elif defined(TARGET_PPC)
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#define QEMU_ARCH QEMU_ARCH_PPC
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#elif defined(TARGET_S390X)
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@ -16,6 +16,7 @@ enum {
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QEMU_ARCH_SH4 = 1024,
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QEMU_ARCH_SPARC = 2048,
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QEMU_ARCH_XTENSA = 4096,
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QEMU_ARCH_OPENRISC = 8192,
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};
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extern const uint32_t arch_type;
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@ -924,6 +924,7 @@ mips-softmmu \
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mipsel-softmmu \
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mips64-softmmu \
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mips64el-softmmu \
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or32-softmmu \
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ppc-softmmu \
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ppcemb-softmmu \
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ppc64-softmmu \
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@ -3520,7 +3521,7 @@ target_arch2=`echo $target | cut -d '-' -f 1`
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target_bigendian="no"
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case "$target_arch2" in
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armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
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armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
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target_bigendian=yes
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;;
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esac
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@ -3636,6 +3637,11 @@ case "$target_arch2" in
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target_phys_bits=64
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target_long_alignment=8
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;;
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or32)
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TARGET_ARCH=openrisc
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TARGET_BASE_ARCH=openrisc
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target_phys_bits=32
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;;
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ppc)
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gdb_xml_files="power-core.xml power-fpu.xml power-altivec.xml power-spe.xml"
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target_phys_bits=64
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@ -3714,7 +3720,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
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case "$target_arch2" in
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alpha | sparc* | xtensa* | ppc*)
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alpha | or32 | sparc* | xtensa* | ppc*)
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echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
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;;
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esac
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@ -3888,6 +3894,10 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
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echo "CONFIG_MIPS_DIS=y" >> $config_target_mak
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echo "CONFIG_MIPS_DIS=y" >> $libdis_config_mak
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;;
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or32)
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echo "CONFIG_OPENRISC_DIS=y" >> $config_target_mak
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echo "CONFIG_OPENRISC_DIS=y" >> $libdis_config_mak
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;;
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ppc*)
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echo "CONFIG_PPC_DIS=y" >> $config_target_mak
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echo "CONFIG_PPC_DIS=y" >> $libdis_config_mak
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@ -225,6 +225,7 @@ int cpu_exec(CPUArchState *env)
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#elif defined(TARGET_LM32)
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#elif defined(TARGET_MICROBLAZE)
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#elif defined(TARGET_MIPS)
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#elif defined(TARGET_OPENRISC)
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#elif defined(TARGET_SH4)
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#elif defined(TARGET_CRIS)
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#elif defined(TARGET_S390X)
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@ -640,6 +641,7 @@ int cpu_exec(CPUArchState *env)
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| env->cc_dest | (env->cc_x << 4);
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#elif defined(TARGET_MICROBLAZE)
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#elif defined(TARGET_MIPS)
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#elif defined(TARGET_OPENRISC)
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#elif defined(TARGET_SH4)
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#elif defined(TARGET_ALPHA)
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#elif defined(TARGET_CRIS)
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@ -0,0 +1,4 @@
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# Default configuration for or32-softmmu
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CONFIG_SERIAL=y
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CONFIG_OPENCORES_ETH=y
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2
elf.h
2
elf.h
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@ -106,6 +106,8 @@ typedef int64_t Elf64_Sxword;
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#define EM_H8S 48 /* Hitachi H8S */
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#define EM_LATTICEMICO32 138 /* LatticeMico32 */
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#define EM_OPENRISC 92 /* OpenCores OpenRISC */
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#define EM_UNICORE32 110 /* UniCore32 */
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/*
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@ -0,0 +1 @@
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obj-y := $(addprefix ../,$(obj-y))
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1
poison.h
1
poison.h
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@ -14,6 +14,7 @@
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#pragma GCC poison TARGET_M68K
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#pragma GCC poison TARGET_MIPS
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#pragma GCC poison TARGET_MIPS64
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#pragma GCC poison TARGET_OPENRISC
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#pragma GCC poison TARGET_PPC
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#pragma GCC poison TARGET_PPCEMB
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#pragma GCC poison TARGET_PPC64
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@ -0,0 +1,3 @@
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obj-$(CONFIG_SOFTMMU) += machine.o
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obj-y += cpu.o interrupt.o mmu.o translate.o
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obj-y += mmu_helper.o
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@ -0,0 +1,220 @@
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/*
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* QEMU OpenRISC CPU
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*
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* Copyright (c) 2012 Jia Liu <proljc@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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/* CPUClass::reset() */
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static void openrisc_cpu_reset(CPUState *s)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(s);
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OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", cpu->env.cpu_index);
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log_cpu_state(&cpu->env, 0);
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}
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occ->parent_reset(s);
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memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
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tlb_flush(&cpu->env, 1);
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/*tb_flush(&cpu->env); FIXME: Do we need it? */
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cpu->env.pc = 0x100;
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cpu->env.sr = SR_FO | SR_SM;
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cpu->env.exception_index = -1;
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cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
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cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
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cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
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cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
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#ifndef CONFIG_USER_ONLY
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cpu->env.picmr = 0x00000000;
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cpu->env.picsr = 0x00000000;
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cpu->env.ttmr = 0x00000000;
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cpu->env.ttcr = 0x00000000;
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#endif
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}
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static inline void set_feature(OpenRISCCPU *cpu, int feature)
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{
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cpu->feature |= feature;
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cpu->env.cpucfgr = cpu->feature;
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}
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void openrisc_cpu_realize(Object *obj, Error **errp)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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qemu_init_vcpu(&cpu->env);
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cpu_reset(CPU(cpu));
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}
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static void openrisc_cpu_initfn(Object *obj)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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static int inited;
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cpu_exec_init(&cpu->env);
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#ifndef CONFIG_USER_ONLY
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cpu_openrisc_mmu_init(cpu);
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#endif
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if (tcg_enabled() && !inited) {
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inited = 1;
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openrisc_translate_init();
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}
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}
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/* CPU models */
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static void or1200_initfn(Object *obj)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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set_feature(cpu, OPENRISC_FEATURE_OB32S);
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set_feature(cpu, OPENRISC_FEATURE_OF32S);
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}
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static void openrisc_any_initfn(Object *obj)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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set_feature(cpu, OPENRISC_FEATURE_OB32S);
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}
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typedef struct OpenRISCCPUInfo {
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const char *name;
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void (*initfn)(Object *obj);
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} OpenRISCCPUInfo;
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static const OpenRISCCPUInfo openrisc_cpus[] = {
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{ .name = "or1200", .initfn = or1200_initfn },
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{ .name = "any", .initfn = openrisc_any_initfn },
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};
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static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
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{
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OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(occ);
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occ->parent_reset = cc->reset;
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cc->reset = openrisc_cpu_reset;
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}
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static void cpu_register(const OpenRISCCPUInfo *info)
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{
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TypeInfo type_info = {
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.name = info->name,
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.parent = TYPE_OPENRISC_CPU,
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.instance_size = sizeof(OpenRISCCPU),
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.instance_init = info->initfn,
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.class_size = sizeof(OpenRISCCPUClass),
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};
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type_register_static(&type_info);
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}
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static const TypeInfo openrisc_cpu_type_info = {
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.name = TYPE_OPENRISC_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(OpenRISCCPU),
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.instance_init = openrisc_cpu_initfn,
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.abstract = false,
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.class_size = sizeof(OpenRISCCPUClass),
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.class_init = openrisc_cpu_class_init,
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};
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static void openrisc_cpu_register_types(void)
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{
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int i;
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type_register_static(&openrisc_cpu_type_info);
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for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
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cpu_register(&openrisc_cpus[i]);
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}
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}
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OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
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{
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OpenRISCCPU *cpu;
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if (!object_class_by_name(cpu_model)) {
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return NULL;
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}
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cpu = OPENRISC_CPU(object_new(cpu_model));
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cpu->env.cpu_model_str = cpu_model;
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openrisc_cpu_realize(OBJECT(cpu), NULL);
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return cpu;
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}
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typedef struct OpenRISCCPUList {
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fprintf_function cpu_fprintf;
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FILE *file;
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} OpenRISCCPUList;
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/* Sort alphabetically by type name, except for "any". */
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static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
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{
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ObjectClass *class_a = (ObjectClass *)a;
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ObjectClass *class_b = (ObjectClass *)b;
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const char *name_a, *name_b;
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name_a = object_class_get_name(class_a);
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name_b = object_class_get_name(class_b);
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if (strcmp(name_a, "any") == 0) {
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return 1;
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} else if (strcmp(name_b, "any") == 0) {
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return -1;
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} else {
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return strcmp(name_a, name_b);
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}
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}
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static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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OpenRISCCPUList *s = user_data;
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(*s->cpu_fprintf)(s->file, " %s\n",
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object_class_get_name(oc));
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}
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void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
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{
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OpenRISCCPUList s = {
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.file = f,
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.cpu_fprintf = cpu_fprintf,
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};
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GSList *list;
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list = object_class_get_list(TYPE_OPENRISC_CPU, false);
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list = g_slist_sort(list, openrisc_cpu_list_compare);
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(*cpu_fprintf)(f, "Available CPUs:\n");
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g_slist_foreach(list, openrisc_cpu_list_entry, &s);
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g_slist_free(list);
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}
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type_init(openrisc_cpu_register_types)
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@ -0,0 +1,335 @@
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/*
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* OpenRISC virtual CPU header.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_OPENRISC_H
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#define CPU_OPENRISC_H
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#define TARGET_LONG_BITS 32
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#define ELF_MACHINE EM_OPENRISC
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#define CPUArchState struct CPUOpenRISCState
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#include "config.h"
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#include "qemu-common.h"
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#include "cpu-defs.h"
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#include "softfloat.h"
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#include "qemu/cpu.h"
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#include "error.h"
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#define TYPE_OPENRISC_CPU "or32-cpu"
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#define OPENRISC_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
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#define OPENRISC_CPU(obj) \
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OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
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#define OPENRISC_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
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/**
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* OpenRISCCPUClass:
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* @parent_reset: The parent class' reset handler.
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*
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* A OpenRISC CPU model.
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*/
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typedef struct OpenRISCCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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void (*parent_reset)(CPUState *cpu);
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} OpenRISCCPUClass;
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#define NB_MMU_MODES 3
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#define TARGET_PAGE_BITS 13
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#define SET_FP_CAUSE(reg, v) do {\
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(reg) = ((reg) & ~(0x3f << 12)) | \
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((v & 0x3f) << 12);\
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} while (0)
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#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
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#define UPDATE_FP_FLAGS(reg, v) do {\
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(reg) |= ((v & 0x1f) << 2);\
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} while (0)
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/* Internal flags, delay slot flag */
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#define D_FLAG 1
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/* Registers */
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enum {
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R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10,
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R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29, R30,
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R31
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};
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/* Register aliases */
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enum {
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R_ZERO = R0,
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R_SP = R1,
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R_FP = R2,
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R_LR = R9,
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R_RV = R11,
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R_RVH = R12
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};
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/* Unit presece register */
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enum {
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UPR_UP = (1 << 0),
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UPR_DCP = (1 << 1),
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UPR_ICP = (1 << 2),
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UPR_DMP = (1 << 3),
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UPR_IMP = (1 << 4),
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UPR_MP = (1 << 5),
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UPR_DUP = (1 << 6),
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UPR_PCUR = (1 << 7),
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UPR_PMP = (1 << 8),
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UPR_PICP = (1 << 9),
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UPR_TTP = (1 << 10),
|
||||
UPR_CUP = (255 << 24),
|
||||
};
|
||||
|
||||
/* CPU configure register */
|
||||
enum {
|
||||
CPUCFGR_NSGF = (15 << 0),
|
||||
CPUCFGR_CGF = (1 << 4),
|
||||
CPUCFGR_OB32S = (1 << 5),
|
||||
CPUCFGR_OB64S = (1 << 6),
|
||||
CPUCFGR_OF32S = (1 << 7),
|
||||
CPUCFGR_OF64S = (1 << 8),
|
||||
CPUCFGR_OV64S = (1 << 9),
|
||||
};
|
||||
|
||||
/* DMMU configure register */
|
||||
enum {
|
||||
DMMUCFGR_NTW = (3 << 0),
|
||||
DMMUCFGR_NTS = (7 << 2),
|
||||
DMMUCFGR_NAE = (7 << 5),
|
||||
DMMUCFGR_CRI = (1 << 8),
|
||||
DMMUCFGR_PRI = (1 << 9),
|
||||
DMMUCFGR_TEIRI = (1 << 10),
|
||||
DMMUCFGR_HTR = (1 << 11),
|
||||
};
|
||||
|
||||
/* IMMU configure register */
|
||||
enum {
|
||||
IMMUCFGR_NTW = (3 << 0),
|
||||
IMMUCFGR_NTS = (7 << 2),
|
||||
IMMUCFGR_NAE = (7 << 5),
|
||||
IMMUCFGR_CRI = (1 << 8),
|
||||
IMMUCFGR_PRI = (1 << 9),
|
||||
IMMUCFGR_TEIRI = (1 << 10),
|
||||
IMMUCFGR_HTR = (1 << 11),
|
||||
};
|
||||
|
||||
/* Float point control status register */
|
||||
enum {
|
||||
FPCSR_FPEE = 1,
|
||||
FPCSR_RM = (3 << 1),
|
||||
FPCSR_OVF = (1 << 3),
|
||||
FPCSR_UNF = (1 << 4),
|
||||
FPCSR_SNF = (1 << 5),
|
||||
FPCSR_QNF = (1 << 6),
|
||||
FPCSR_ZF = (1 << 7),
|
||||
FPCSR_IXF = (1 << 8),
|
||||
FPCSR_IVF = (1 << 9),
|
||||
FPCSR_INF = (1 << 10),
|
||||
FPCSR_DZF = (1 << 11),
|
||||
};
|
||||
|
||||
/* Exceptions indices */
|
||||
enum {
|
||||
EXCP_RESET = 0x1,
|
||||
EXCP_BUSERR = 0x2,
|
||||
EXCP_DPF = 0x3,
|
||||
EXCP_IPF = 0x4,
|
||||
EXCP_TICK = 0x5,
|
||||
EXCP_ALIGN = 0x6,
|
||||
EXCP_ILLEGAL = 0x7,
|
||||
EXCP_INT = 0x8,
|
||||
EXCP_DTLBMISS = 0x9,
|
||||
EXCP_ITLBMISS = 0xa,
|
||||
EXCP_RANGE = 0xb,
|
||||
EXCP_SYSCALL = 0xc,
|
||||
EXCP_FPE = 0xd,
|
||||
EXCP_TRAP = 0xe,
|
||||
EXCP_NR,
|
||||
};
|
||||
|
||||
/* Supervisor register */
|
||||
enum {
|
||||
SR_SM = (1 << 0),
|
||||
SR_TEE = (1 << 1),
|
||||
SR_IEE = (1 << 2),
|
||||
SR_DCE = (1 << 3),
|
||||
SR_ICE = (1 << 4),
|
||||
SR_DME = (1 << 5),
|
||||
SR_IME = (1 << 6),
|
||||
SR_LEE = (1 << 7),
|
||||
SR_CE = (1 << 8),
|
||||
SR_F = (1 << 9),
|
||||
SR_CY = (1 << 10),
|
||||
SR_OV = (1 << 11),
|
||||
SR_OVE = (1 << 12),
|
||||
SR_DSX = (1 << 13),
|
||||
SR_EPH = (1 << 14),
|
||||
SR_FO = (1 << 15),
|
||||
SR_SUMRA = (1 << 16),
|
||||
SR_SCE = (1 << 17),
|
||||
};
|
||||
|
||||
/* OpenRISC Hardware Capabilities */
|
||||
enum {
|
||||
OPENRISC_FEATURE_NSGF = (15 << 0),
|
||||
OPENRISC_FEATURE_CGF = (1 << 4),
|
||||
OPENRISC_FEATURE_OB32S = (1 << 5),
|
||||
OPENRISC_FEATURE_OB64S = (1 << 6),
|
||||
OPENRISC_FEATURE_OF32S = (1 << 7),
|
||||
OPENRISC_FEATURE_OF64S = (1 << 8),
|
||||
OPENRISC_FEATURE_OV64S = (1 << 9),
|
||||
};
|
||||
|
||||
typedef struct CPUOpenRISCState {
|
||||
target_ulong gpr[32]; /* General registers */
|
||||
target_ulong pc; /* Program counter */
|
||||
target_ulong npc; /* Next PC */
|
||||
target_ulong ppc; /* Prev PC */
|
||||
target_ulong jmp_pc; /* Jump PC */
|
||||
|
||||
target_ulong machi; /* Multiply register MACHI */
|
||||
target_ulong maclo; /* Multiply register MACLO */
|
||||
|
||||
target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI */
|
||||
target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO */
|
||||
|
||||
target_ulong epcr; /* Exception PC register */
|
||||
target_ulong eear; /* Exception EA register */
|
||||
|
||||
uint32_t sr; /* Supervisor register */
|
||||
uint32_t vr; /* Version register */
|
||||
uint32_t upr; /* Unit presence register */
|
||||
uint32_t cpucfgr; /* CPU configure register */
|
||||
uint32_t dmmucfgr; /* DMMU configure register */
|
||||
uint32_t immucfgr; /* IMMU configure register */
|
||||
uint32_t esr; /* Exception supervisor register */
|
||||
uint32_t fpcsr; /* Float register */
|
||||
float_status fp_status;
|
||||
|
||||
uint32_t flags; /* cpu_flags, we only use it for exception
|
||||
in solt so far. */
|
||||
uint32_t btaken; /* the SR_F bit */
|
||||
|
||||
CPU_COMMON
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
struct QEMUTimer *timer;
|
||||
uint32_t ttmr; /* Timer tick mode register */
|
||||
uint32_t ttcr; /* Timer tick count register */
|
||||
|
||||
uint32_t picmr; /* Interrupt mask register */
|
||||
uint32_t picsr; /* Interrupt contrl register*/
|
||||
#endif
|
||||
} CPUOpenRISCState;
|
||||
|
||||
/**
|
||||
* OpenRISCCPU:
|
||||
* @env: #CPUOpenRISCState
|
||||
*
|
||||
* A OpenRISC CPU.
|
||||
*/
|
||||
typedef struct OpenRISCCPU {
|
||||
/*< private >*/
|
||||
CPUState parent_obj;
|
||||
/*< public >*/
|
||||
|
||||
CPUOpenRISCState env;
|
||||
|
||||
uint32_t feature; /* CPU Capabilities */
|
||||
} OpenRISCCPU;
|
||||
|
||||
static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
|
||||
{
|
||||
return OPENRISC_CPU(container_of(env, OpenRISCCPU, env));
|
||||
}
|
||||
|
||||
#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
|
||||
|
||||
OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
|
||||
void openrisc_cpu_realize(Object *obj, Error **errp);
|
||||
|
||||
void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
|
||||
int cpu_openrisc_exec(CPUOpenRISCState *s);
|
||||
void do_interrupt(CPUOpenRISCState *env);
|
||||
void openrisc_translate_init(void);
|
||||
|
||||
#define cpu_list cpu_openrisc_list
|
||||
#define cpu_exec cpu_openrisc_exec
|
||||
#define cpu_gen_code cpu_openrisc_gen_code
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
|
||||
#endif
|
||||
|
||||
static inline CPUOpenRISCState *cpu_init(const char *cpu_model)
|
||||
{
|
||||
OpenRISCCPU *cpu = cpu_openrisc_init(cpu_model);
|
||||
if (cpu) {
|
||||
return &cpu->env;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#include "cpu-all.h"
|
||||
|
||||
static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
|
||||
target_ulong *pc,
|
||||
target_ulong *cs_base, int *flags)
|
||||
{
|
||||
*pc = env->pc;
|
||||
*cs_base = 0;
|
||||
/* D_FLAG -- branch instruction exception */
|
||||
*flags = (env->flags & D_FLAG);
|
||||
}
|
||||
|
||||
static inline int cpu_mmu_index(CPUOpenRISCState *env)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline bool cpu_has_work(CPUOpenRISCState *env)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
#include "exec-all.h"
|
||||
|
||||
static inline target_ulong cpu_get_pc(CPUOpenRISCState *env)
|
||||
{
|
||||
return env->pc;
|
||||
}
|
||||
|
||||
static inline void cpu_pc_from_tb(CPUOpenRISCState *env, TranslationBlock *tb)
|
||||
{
|
||||
env->pc = tb->pc;
|
||||
}
|
||||
|
||||
#endif /* CPU_OPENRISC_H */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* OpenRISC interrupt.
|
||||
*
|
||||
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
#include "qemu-common.h"
|
||||
#include "gdbstub.h"
|
||||
#include "host-utils.h"
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
#include "hw/loader.h"
|
||||
#endif
|
||||
|
||||
void do_interrupt(CPUOpenRISCState *env)
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* OpenRISC Machine
|
||||
*
|
||||
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "hw/hw.h"
|
||||
#include "hw/boards.h"
|
||||
|
||||
static const VMStateDescription vmstate_cpu = {
|
||||
.name = "cpu",
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32_ARRAY(gpr, CPUOpenRISCState, 32),
|
||||
VMSTATE_UINT32(sr, CPUOpenRISCState),
|
||||
VMSTATE_UINT32(epcr, CPUOpenRISCState),
|
||||
VMSTATE_UINT32(eear, CPUOpenRISCState),
|
||||
VMSTATE_UINT32(esr, CPUOpenRISCState),
|
||||
VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
|
||||
VMSTATE_UINT32(pc, CPUOpenRISCState),
|
||||
VMSTATE_UINT32(npc, CPUOpenRISCState),
|
||||
VMSTATE_UINT32(ppc, CPUOpenRISCState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
void cpu_save(QEMUFile *f, void *opaque)
|
||||
{
|
||||
vmstate_save_state(f, &vmstate_cpu, opaque);
|
||||
}
|
||||
|
||||
int cpu_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
|
||||
}
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* OpenRISC MMU.
|
||||
*
|
||||
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
|
||||
* Zhizhou Zhang <etouzh@gmail.com>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
#include "qemu-common.h"
|
||||
#include "gdbstub.h"
|
||||
#include "host-utils.h"
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
#include "hw/loader.h"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
target_phys_addr_t cpu_get_phys_page_debug(CPUOpenRISCState *env,
|
||||
target_ulong addr)
|
||||
{
|
||||
return addr;
|
||||
}
|
||||
|
||||
void cpu_openrisc_mmu_init(OpenRISCCPU *cpu)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* OpenRISC MMU helper routines
|
||||
*
|
||||
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
|
||||
* Zhizhou Zhang <etouzh@gmail.com>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
#include "softmmu_exec.h"
|
||||
#define MMUSUFFIX _mmu
|
||||
|
||||
#define SHIFT 0
|
||||
#include "softmmu_template.h"
|
||||
|
||||
#define SHIFT 1
|
||||
#include "softmmu_template.h"
|
||||
|
||||
#define SHIFT 2
|
||||
#include "softmmu_template.h"
|
||||
|
||||
#define SHIFT 3
|
||||
#include "softmmu_template.h"
|
||||
|
||||
void tlb_fill(CPUOpenRISCState *env, target_ulong addr, int is_write,
|
||||
int mmu_idx, uintptr_t retaddr)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* OpenRISC translation
|
||||
*
|
||||
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
|
||||
* Feng Gao <gf91597@gmail.com>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
#include "exec-all.h"
|
||||
#include "disas.h"
|
||||
#include "tcg-op.h"
|
||||
#include "qemu-common.h"
|
||||
#include "qemu-log.h"
|
||||
#include "config.h"
|
||||
|
||||
#define OPENRISC_DISAS
|
||||
|
||||
#ifdef OPENRISC_DISAS
|
||||
# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
|
||||
#else
|
||||
# define LOG_DIS(...) do { } while (0)
|
||||
#endif
|
||||
|
||||
void openrisc_translate_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
|
||||
TranslationBlock *tb,
|
||||
int search_pc)
|
||||
{
|
||||
}
|
||||
|
||||
void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
|
||||
{
|
||||
gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 0);
|
||||
}
|
||||
|
||||
void gen_intermediate_code_pc(CPUOpenRISCState *env,
|
||||
struct TranslationBlock *tb)
|
||||
{
|
||||
gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 1);
|
||||
}
|
||||
|
||||
void cpu_dump_state(CPUOpenRISCState *env, FILE *f,
|
||||
fprintf_function cpu_fprintf,
|
||||
int flags)
|
||||
{
|
||||
int i;
|
||||
uint32_t *regs = env->gpr;
|
||||
cpu_fprintf(f, "PC=%08x\n", env->pc);
|
||||
for (i = 0; i < 32; ++i) {
|
||||
cpu_fprintf(f, "R%02d=%08x%c", i, regs[i],
|
||||
(i % 4) == 3 ? '\n' : ' ');
|
||||
}
|
||||
}
|
||||
|
||||
void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb,
|
||||
int pc_pos)
|
||||
{
|
||||
env->pc = gen_opc_pc[pc_pos];
|
||||
}
|
||||
Loading…
Reference in New Issue