nvic: Make SHPR registers banked
Make the set_prio() function take a bool indicating whether to pend the secure or non-secure version of a banked interrupt, and use this to implement the correct banking semantics for the SHPR registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-11-git-send-email-peter.maydell@linaro.org
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@ -349,15 +349,40 @@ int armv7m_nvic_raw_execution_priority(void *opaque)
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return s->exception_prio;
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}
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/* caller must call nvic_irq_update() after this */
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static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
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/* caller must call nvic_irq_update() after this.
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* secure indicates the bank to use for banked exceptions (we assert if
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* we are passed secure=true for a non-banked exception).
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*/
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static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)
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{
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assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
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assert(irq < s->num_irq);
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s->vectors[irq].prio = prio;
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if (secure) {
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assert(exc_is_banked(irq));
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s->sec_vectors[irq].prio = prio;
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} else {
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s->vectors[irq].prio = prio;
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}
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trace_nvic_set_prio(irq, prio);
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trace_nvic_set_prio(irq, secure, prio);
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}
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/* Return the current raw priority register value.
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* secure indicates the bank to use for banked exceptions (we assert if
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* we are passed secure=true for a non-banked exception).
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*/
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static int get_prio(NVICState *s, unsigned irq, bool secure)
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{
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assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
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assert(irq < s->num_irq);
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if (secure) {
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assert(exc_is_banked(irq));
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return s->sec_vectors[irq].prio;
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} else {
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return s->vectors[irq].prio;
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}
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}
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/* Recompute state and assert irq line accordingly.
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@ -1149,6 +1174,47 @@ static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)
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}
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}
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static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs)
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{
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/* Behaviour for the SHPR register field for this exception:
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* return M_REG_NS to use the nonsecure vector (including for
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* non-banked exceptions), M_REG_S for the secure version of
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* a banked exception, and -1 if this field should RAZ/WI.
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*/
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switch (exc) {
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case ARMV7M_EXCP_MEM:
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case ARMV7M_EXCP_USAGE:
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case ARMV7M_EXCP_SVC:
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case ARMV7M_EXCP_PENDSV:
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case ARMV7M_EXCP_SYSTICK:
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/* Banked exceptions */
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return attrs.secure;
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case ARMV7M_EXCP_BUS:
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/* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
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if (!attrs.secure &&
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!(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
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return -1;
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}
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return M_REG_NS;
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case ARMV7M_EXCP_SECURE:
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/* Not banked, RAZ/WI from nonsecure */
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if (!attrs.secure) {
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return -1;
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}
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return M_REG_NS;
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case ARMV7M_EXCP_DEBUG:
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/* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
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return M_REG_NS;
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case 8 ... 10:
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case 13:
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/* RES0 */
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return -1;
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default:
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/* Not reachable due to decode of SHPR register addresses */
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g_assert_not_reached();
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}
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}
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static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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@ -1213,10 +1279,16 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
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}
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}
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break;
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case 0xd18 ... 0xd23: /* System Handler Priority. */
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case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
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val = 0;
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for (i = 0; i < size; i++) {
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val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);
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unsigned hdlidx = (offset - 0xd14) + i;
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int sbank = shpr_bank(s, hdlidx, attrs);
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if (sbank < 0) {
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continue;
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}
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val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
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}
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break;
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case 0xfe0 ... 0xfff: /* ID. */
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@ -1299,15 +1371,21 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
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for (i = 0; i < size && startvec + i < s->num_irq; i++) {
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if (attrs.secure || s->itns[startvec + i]) {
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set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
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set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);
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}
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}
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nvic_irq_update(s);
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return MEMTX_OK;
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case 0xd18 ... 0xd23: /* System Handler Priority. */
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case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
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for (i = 0; i < size; i++) {
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unsigned hdlidx = (offset - 0xd14) + i;
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set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);
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int newprio = extract32(value, i * 8, 8);
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int sbank = shpr_bank(s, hdlidx, attrs);
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if (sbank < 0) {
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continue;
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}
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set_prio(s, hdlidx, sbank, newprio);
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}
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nvic_irq_update(s);
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return MEMTX_OK;
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@ -169,7 +169,7 @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
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# hw/intc/armv7m_nvic.c
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nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
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nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
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nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
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nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %d priority %d"
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nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
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nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
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nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
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