tpm_tis: move r/w_offsets to TPMState
Now that we have a single buffer, we also only need a single set of read/write offsets into that buffer. This works since only one locality can be active. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
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@ -61,9 +61,6 @@ typedef struct TPMLocality {
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uint32_t iface_id;
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uint32_t inte;
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uint32_t ints;
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uint16_t w_offset;
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uint16_t r_offset;
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} TPMLocality;
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typedef struct TPMState {
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@ -71,6 +68,8 @@ typedef struct TPMState {
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MemoryRegion mmio;
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unsigned char buffer[TPM_TIS_BUFFER_MAX];
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uint16_t w_offset;
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uint16_t r_offset;
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uint8_t active_locty;
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uint8_t aborting_locty;
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@ -254,8 +253,6 @@ static void tpm_tis_sts_set(TPMLocality *l, uint32_t flags)
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*/
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static void tpm_tis_tpm_send(TPMState *s, uint8_t locty)
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{
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TPMLocality *locty_data = &s->loc[locty];
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tpm_tis_show_buffer(s->buffer, s->be_buffer_size,
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"tpm_tis: To TPM");
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@ -268,7 +265,7 @@ static void tpm_tis_tpm_send(TPMState *s, uint8_t locty)
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s->cmd = (TPMBackendCmd) {
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.locty = locty,
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.in = s->buffer,
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.in_len = locty_data->w_offset,
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.in_len = s->w_offset,
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.out = s->buffer,
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.out_len = s->be_buffer_size,
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};
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@ -350,8 +347,8 @@ static void tpm_tis_new_active_locality(TPMState *s, uint8_t new_active_locty)
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/* abort -- this function switches the locality */
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static void tpm_tis_abort(TPMState *s, uint8_t locty)
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{
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s->loc[locty].r_offset = 0;
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s->loc[locty].w_offset = 0;
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s->r_offset = 0;
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s->w_offset = 0;
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DPRINTF("tpm_tis: tis_abort: new active locality is %d\n", s->next_locty);
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@ -418,8 +415,8 @@ static void tpm_tis_request_completed(TPMIf *ti)
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tpm_tis_sts_set(&s->loc[locty],
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TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE);
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s->loc[locty].state = TPM_TIS_STATE_COMPLETION;
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s->loc[locty].r_offset = 0;
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s->loc[locty].w_offset = 0;
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s->r_offset = 0;
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s->w_offset = 0;
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tpm_tis_show_buffer(s->buffer, s->be_buffer_size,
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"tpm_tis: From TPM");
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@ -444,14 +441,14 @@ static uint32_t tpm_tis_data_read(TPMState *s, uint8_t locty)
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len = MIN(tpm_cmd_get_size(&s->buffer),
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s->be_buffer_size);
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ret = s->buffer[s->loc[locty].r_offset++];
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if (s->loc[locty].r_offset >= len) {
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ret = s->buffer[s->r_offset++];
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if (s->r_offset >= len) {
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/* got last byte */
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tpm_tis_sts_set(&s->loc[locty], TPM_TIS_STS_VALID);
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tpm_tis_raise_irq(s, locty, TPM_TIS_INT_STS_VALID);
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}
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DPRINTF("tpm_tis: tpm_tis_data_read byte 0x%02x [%d]\n",
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ret, s->loc[locty].r_offset - 1);
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ret, s->r_offset - 1);
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}
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return ret;
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@ -488,24 +485,24 @@ static void tpm_tis_dump_state(void *opaque, hwaddr addr)
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DPRINTF("tpm_tis: read offset : %d\n"
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"tpm_tis: result buffer : ",
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s->loc[locty].r_offset);
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s->r_offset);
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for (idx = 0;
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idx < MIN(tpm_cmd_get_size(&s->buffer), s->be_buffer_size);
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idx++) {
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DPRINTF("%c%02x%s",
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s->loc[locty].r_offset == idx ? '>' : ' ',
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s->r_offset == idx ? '>' : ' ',
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s->buffer[idx],
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((idx & 0xf) == 0xf) ? "\ntpm_tis: " : "");
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}
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DPRINTF("\n"
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"tpm_tis: write offset : %d\n"
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"tpm_tis: request buffer: ",
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s->loc[locty].w_offset);
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s->w_offset);
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for (idx = 0;
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idx < MIN(tpm_cmd_get_size(s->buffer), s->be_buffer_size);
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idx++) {
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DPRINTF("%c%02x%s",
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s->loc[locty].w_offset == idx ? '>' : ' ',
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s->w_offset == idx ? '>' : ' ',
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s->buffer[idx],
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((idx & 0xf) == 0xf) ? "\ntpm_tis: " : "");
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}
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@ -570,9 +567,9 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr,
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val = TPM_TIS_BURST_COUNT(
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MIN(tpm_cmd_get_size(&s->buffer),
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s->be_buffer_size)
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- s->loc[locty].r_offset) | s->loc[locty].sts;
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- s->r_offset) | s->loc[locty].sts;
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} else {
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avail = s->be_buffer_size - s->loc[locty].w_offset;
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avail = s->be_buffer_size - s->w_offset;
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/*
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* byte-sized reads should not return 0x00 for 0x100
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* available bytes.
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@ -836,8 +833,8 @@ static void tpm_tis_mmio_write(void *opaque, hwaddr addr,
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switch (s->loc[locty].state) {
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case TPM_TIS_STATE_READY:
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s->loc[locty].w_offset = 0;
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s->loc[locty].r_offset = 0;
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s->w_offset = 0;
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s->r_offset = 0;
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break;
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case TPM_TIS_STATE_IDLE:
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@ -855,8 +852,8 @@ static void tpm_tis_mmio_write(void *opaque, hwaddr addr,
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break;
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case TPM_TIS_STATE_COMPLETION:
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s->loc[locty].w_offset = 0;
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s->loc[locty].r_offset = 0;
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s->w_offset = 0;
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s->r_offset = 0;
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/* shortcut to ready state with C/R set */
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s->loc[locty].state = TPM_TIS_STATE_READY;
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if (!(s->loc[locty].sts & TPM_TIS_STS_COMMAND_READY)) {
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@ -882,7 +879,7 @@ static void tpm_tis_mmio_write(void *opaque, hwaddr addr,
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} else if (val == TPM_TIS_STS_RESPONSE_RETRY) {
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switch (s->loc[locty].state) {
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case TPM_TIS_STATE_COMPLETION:
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s->loc[locty].r_offset = 0;
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s->r_offset = 0;
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tpm_tis_sts_set(&s->loc[locty],
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TPM_TIS_STS_VALID|
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TPM_TIS_STS_DATA_AVAILABLE);
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@ -920,8 +917,8 @@ static void tpm_tis_mmio_write(void *opaque, hwaddr addr,
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}
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while ((s->loc[locty].sts & TPM_TIS_STS_EXPECT) && size > 0) {
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if (s->loc[locty].w_offset < s->be_buffer_size) {
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s->buffer[s->loc[locty].w_offset++] =
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if (s->w_offset < s->be_buffer_size) {
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s->buffer[s->w_offset++] =
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(uint8_t)val;
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val >>= 8;
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size--;
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@ -931,13 +928,13 @@ static void tpm_tis_mmio_write(void *opaque, hwaddr addr,
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}
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/* check for complete packet */
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if (s->loc[locty].w_offset > 5 &&
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if (s->w_offset > 5 &&
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(s->loc[locty].sts & TPM_TIS_STS_EXPECT)) {
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/* we have a packet length - see if we have all of it */
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bool need_irq = !(s->loc[locty].sts & TPM_TIS_STS_VALID);
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len = tpm_cmd_get_size(&s->buffer);
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if (len > s->loc[locty].w_offset) {
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if (len > s->w_offset) {
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tpm_tis_sts_set(&s->loc[locty],
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TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID);
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} else {
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@ -1026,8 +1023,8 @@ static void tpm_tis_reset(DeviceState *dev)
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s->loc[c].ints = 0;
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s->loc[c].state = TPM_TIS_STATE_IDLE;
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s->loc[c].w_offset = 0;
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s->loc[c].r_offset = 0;
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s->w_offset = 0;
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s->r_offset = 0;
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}
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tpm_tis_do_startup_tpm(s, s->be_buffer_size);
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