bios: disable processor SSDT generation. Fixes high idle load on
x86/x86-64. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4270 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
aa92310171
commit
e6e514c529
BIN
pc-bios/bios.bin
BIN
pc-bios/bios.bin
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@ -1,14 +1,14 @@
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Index: rombios.c
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/rombios.c,v
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retrieving revision 1.205
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diff -u -d -p -r1.205 rombios.c
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--- rombios.c 21 Mar 2008 19:06:31 -0000 1.205
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+++ rombios.c 10 Apr 2008 09:47:48 -0000
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@@ -4395,22 +4395,25 @@ BX_DEBUG_INT15("case default:\n");
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retrieving revision 1.207
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diff -u -d -p -r1.207 rombios.c
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--- rombios.c 21 Apr 2008 14:22:01 -0000 1.207
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+++ rombios.c 27 Apr 2008 23:40:19 -0000
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@@ -4404,22 +4404,25 @@ BX_DEBUG_INT15("case default:\n");
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#endif // BX_USE_PS2_MOUSE
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-void set_e820_range(ES, DI, start, end, type)
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+void set_e820_range(ES, DI, start, end, extra_start, extra_end, type)
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Bit16u ES;
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@ -24,7 +24,7 @@ diff -u -d -p -r1.205 rombios.c
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- write_word(ES, DI+4, 0x00);
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+ write_word(ES, DI+4, extra_start);
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write_word(ES, DI+6, 0x00);
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end -= start;
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+ extra_end -= extra_start;
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write_word(ES, DI+8, end);
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@ -32,22 +32,22 @@ diff -u -d -p -r1.205 rombios.c
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- write_word(ES, DI+12, 0x0000);
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+ write_word(ES, DI+12, extra_end);
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write_word(ES, DI+14, 0x0000);
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write_word(ES, DI+16, type);
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@@ -4423,7 +4426,9 @@ int15_function32(regs, ES, DS, FLAGS)
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@@ -4432,7 +4435,9 @@ int15_function32(regs, ES, DS, FLAGS)
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Bit16u ES, DS, FLAGS;
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{
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Bit32u extended_memory_size=0; // 64bits long
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+ Bit32u extra_lowbits_memory_size=0;
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Bit16u CX,DX;
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+ Bit8u extra_highbits_memory_size=0;
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BX_DEBUG_INT15("int15 AX=%04x\n",regs.u.r16.ax);
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@@ -4497,11 +4502,18 @@ ASM_END
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@@ -4506,11 +4511,18 @@ ASM_END
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extended_memory_size += (1L * 1024 * 1024);
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}
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+ extra_lowbits_memory_size = inb_cmos(0x5c);
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+ extra_lowbits_memory_size <<= 8;
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+ extra_lowbits_memory_size |= inb_cmos(0x5b);
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@ -64,7 +64,7 @@ diff -u -d -p -r1.205 rombios.c
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regs.u.r32.ebx = 1;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4510,7 +4522,7 @@ ASM_END
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@@ -4519,7 +4531,7 @@ ASM_END
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break;
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case 1:
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set_e820_range(ES, regs.u.r16.di,
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@ -73,7 +73,7 @@ diff -u -d -p -r1.205 rombios.c
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regs.u.r32.ebx = 2;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4519,7 +4531,7 @@ ASM_END
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@@ -4528,7 +4540,7 @@ ASM_END
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break;
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case 2:
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set_e820_range(ES, regs.u.r16.di,
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@ -82,16 +82,16 @@ diff -u -d -p -r1.205 rombios.c
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regs.u.r32.ebx = 3;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4529,7 +4541,7 @@ ASM_END
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case 3:
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@@ -4539,7 +4551,7 @@ ASM_END
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#if BX_ROMBIOS32
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set_e820_range(ES, regs.u.r16.di,
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0x00100000L,
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- extended_memory_size - ACPI_DATA_SIZE, 1);
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+ extended_memory_size - ACPI_DATA_SIZE ,0, 0, 1);
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regs.u.r32.ebx = 4;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4539,7 +4551,7 @@ ASM_END
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#else
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set_e820_range(ES, regs.u.r16.di,
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@@ -4555,7 +4567,7 @@ ASM_END
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case 4:
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set_e820_range(ES, regs.u.r16.di,
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extended_memory_size - ACPI_DATA_SIZE,
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@ -100,7 +100,7 @@ diff -u -d -p -r1.205 rombios.c
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regs.u.r32.ebx = 5;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4549,7 +4561,20 @@ ASM_END
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@@ -4565,7 +4577,20 @@ ASM_END
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case 5:
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/* 256KB BIOS area at the end of 4 GB */
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set_e820_range(ES, regs.u.r16.di,
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@ -128,7 +128,7 @@ RCS file: /cvsroot/bochs/bochs/bios/rombios.h,v
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retrieving revision 1.6
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diff -u -d -p -r1.6 rombios.h
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--- rombios.h 26 Jan 2008 09:15:27 -0000 1.6
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+++ rombios.h 10 Apr 2008 09:47:48 -0000
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+++ rombios.h 27 Apr 2008 23:40:19 -0000
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@@ -19,7 +19,7 @@
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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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@ -141,11 +141,11 @@ diff -u -d -p -r1.6 rombios.h
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Index: rombios32.c
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v
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retrieving revision 1.24
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diff -u -d -p -r1.24 rombios32.c
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--- rombios32.c 6 Mar 2008 20:18:20 -0000 1.24
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+++ rombios32.c 10 Apr 2008 09:47:48 -0000
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@@ -477,7 +477,12 @@ void smp_probe(void)
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retrieving revision 1.26
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diff -u -d -p -r1.26 rombios32.c
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--- rombios32.c 8 Apr 2008 16:41:18 -0000 1.26
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+++ rombios32.c 27 Apr 2008 23:40:19 -0000
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@@ -478,7 +478,12 @@ void smp_probe(void)
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sipi_vector = AP_BOOT_ADDR >> 12;
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writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
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@ -158,19 +158,42 @@ diff -u -d -p -r1.24 rombios32.c
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smp_cpus = readw((void *)CPU_COUNT_ADDR);
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}
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Index: rombios32start.S
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/rombios32start.S,v
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retrieving revision 1.4
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diff -u -d -p -r1.4 rombios32start.S
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--- rombios32start.S 26 Jan 2008 09:15:27 -0000 1.4
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+++ rombios32start.S 10 Apr 2008 09:47:48 -0000
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@@ -42,7 +42,7 @@ _start:
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smp_ap_boot_code_start:
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xor %ax, %ax
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mov %ax, %ds
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- incw CPU_COUNT_ADDR
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+ lock incw CPU_COUNT_ADDR
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1:
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hlt
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jmp 1b
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@@ -1081,7 +1086,7 @@ struct rsdp_descriptor /* Root S
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struct rsdt_descriptor_rev1
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{
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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- uint32_t table_offset_entry [3]; /* Array of pointers to other */
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+ uint32_t table_offset_entry [2]; /* Array of pointers to other */
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/* ACPI tables */
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};
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@@ -1335,8 +1340,8 @@ void acpi_bios_init(void)
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struct fadt_descriptor_rev1 *fadt;
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struct facs_descriptor_rev1 *facs;
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struct multiple_apic_table *madt;
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- uint8_t *dsdt, *ssdt;
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- uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
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+ uint8_t *dsdt;
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+ uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr;
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uint32_t acpi_tables_size, madt_addr, madt_size;
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int i;
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@@ -1370,10 +1375,6 @@ void acpi_bios_init(void)
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dsdt = (void *)(addr);
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addr += sizeof(AmlCode);
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- ssdt_addr = addr;
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- ssdt = (void *)(addr);
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- addr += acpi_build_processor_ssdt(ssdt);
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-
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addr = (addr + 7) & ~7;
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madt_addr = addr;
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madt_size = sizeof(*madt) +
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@@ -1403,7 +1404,6 @@ void acpi_bios_init(void)
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memset(rsdt, 0, sizeof(*rsdt));
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rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
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rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
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- rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
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acpi_build_table_header((struct acpi_table_header *)rsdt,
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"RSDT", sizeof(*rsdt), 1);
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