target/arm: Convert T16, extract
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-57-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -23,6 +23,7 @@
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&s_rrr_shr !extern s rn rd rm rs shty
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&s_rri_rot !extern s rn rd imm rot
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&s_rrrr !extern s rd rn rm ra
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&rrr_rot !extern rd rn rm rot
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&ri !extern rd imm
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&r !extern rm
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&ldst_rr !extern p w u rn rt rm shimm shtype
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@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branchr
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BLX_r 0100 0111 1 .... 000 @branchr
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BXNS 0100 0111 0 .... 100 @branchr
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BLXNS 0100 0111 1 .... 100 @branchr
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# Extend
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@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0
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SXTAH 1011 0010 00 ... ... @extend
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SXTAB 1011 0010 01 ... ... @extend
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UXTAH 1011 0010 10 ... ... @extend
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UXTAB 1011 0010 11 ... ... @extend
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@ -10766,21 +10766,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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op = (insn >> 8) & 0xf;
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switch (op) {
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case 0: /* add/sub (sp, immediate), in decodetree */
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case 2: /* sign/zero extend, in decodetree */
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goto illegal_op;
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case 2: /* sign/zero extend. */
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ARCH(6);
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rd = insn & 7;
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rm = (insn >> 3) & 7;
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tmp = load_reg(s, rm);
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switch ((insn >> 6) & 3) {
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case 0: gen_sxth(tmp); break;
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case 1: gen_sxtb(tmp); break;
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case 2: gen_uxth(tmp); break;
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case 3: gen_uxtb(tmp); break;
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}
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store_reg(s, rd, tmp);
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break;
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case 4: case 5: case 0xc: case 0xd:
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/*
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* 0b1011_x10x_xxxx_xxxx
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