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hw/armv7m_nvic: Use LOG_GUEST_ERROR and LOG_UNIMP

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Use LOG_GUEST_ERROR and LOG_UNIMP rather than hw_error() where
appropriate.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2012-10-30 07:45:10 +00:00
parent edb94a41e3
commit e72e3ffc3d
1 changed files with 19 additions and 12 deletions
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31
hw/armv7m_nvic.c
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@ -234,7 +234,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
return val; return val;
case 0xd28: /* Configurable Fault Status. */ case 0xd28: /* Configurable Fault Status. */
/* TODO: Implement Fault Status. */ /* TODO: Implement Fault Status. */
hw_error("Not implemented: Configurable Fault Status."); qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n");
return 0; return 0;
case 0xd2c: /* Hard Fault Status. */ case 0xd2c: /* Hard Fault Status. */
case 0xd30: /* Debug Fault Status. */ case 0xd30: /* Debug Fault Status. */
@ -242,7 +242,8 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
case 0xd38: /* Bus Fault Address. */ case 0xd38: /* Bus Fault Address. */
case 0xd3c: /* Aux Fault Status. */ case 0xd3c: /* Aux Fault Status. */
/* TODO: Implement fault status registers. */ /* TODO: Implement fault status registers. */
goto bad_reg; qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n");
return 0;
case 0xd40: /* PFR0. */ case 0xd40: /* PFR0. */
return 0x00000030; return 0x00000030;
case 0xd44: /* PRF1. */ case 0xd44: /* PRF1. */
@ -271,8 +272,8 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
return 0x01310102; return 0x01310102;
/* TODO: Implement debug registers. */ /* TODO: Implement debug registers. */
default: default:
bad_reg: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
hw_error("NVIC: Bad read offset 0x%x\n", offset); return 0;
} }
} }
@ -335,17 +336,18 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
case 0xd0c: /* Application Interrupt/Reset Control. */ case 0xd0c: /* Application Interrupt/Reset Control. */
if ((value >> 16) == 0x05fa) { if ((value >> 16) == 0x05fa) {
if (value & 2) { if (value & 2) {
hw_error("VECTCLRACTIVE not implemented"); qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n");
} }
if (value & 5) { if (value & 5) {
hw_error("System reset"); qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");
} }
} }
break; break;
case 0xd10: /* System Control. */ case 0xd10: /* System Control. */
case 0xd14: /* Configuration Control. */ case 0xd14: /* Configuration Control. */
/* TODO: Implement control registers. */ /* TODO: Implement control registers. */
goto bad_reg; qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n");
break;
case 0xd24: /* System Handler Control. */ case 0xd24: /* System Handler Control. */
/* TODO: Real hardware allows you to set/clear the active bits /* TODO: Real hardware allows you to set/clear the active bits
under some circumstances. We don't implement this. */ under some circumstances. We don't implement this. */
@ -359,15 +361,17 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
case 0xd34: /* Mem Manage Address. */ case 0xd34: /* Mem Manage Address. */
case 0xd38: /* Bus Fault Address. */ case 0xd38: /* Bus Fault Address. */
case 0xd3c: /* Aux Fault Status. */ case 0xd3c: /* Aux Fault Status. */
goto bad_reg; qemu_log_mask(LOG_UNIMP,
"NVIC: fault status registers unimplemented\n");
break;
case 0xf00: /* Software Triggered Interrupt Register */ case 0xf00: /* Software Triggered Interrupt Register */
if ((value & 0x1ff) < s->num_irq) { if ((value & 0x1ff) < s->num_irq) {
gic_set_pending_private(&s->gic, 0, value & 0x1ff); gic_set_pending_private(&s->gic, 0, value & 0x1ff);
} }
break; break;
default: default:
bad_reg: qemu_log_mask(LOG_GUEST_ERROR,
hw_error("NVIC: Bad write offset 0x%x\n", offset); "NVIC: Bad write offset 0x%x\n", offset);
} }
} }
@ -395,7 +399,9 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
if (size == 4) { if (size == 4) {
return nvic_readl(s, offset); return nvic_readl(s, offset);
} }
hw_error("NVIC: Bad read of size %d at offset 0x%x\n", size, offset); qemu_log_mask(LOG_GUEST_ERROR,
"NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
return 0;
} }
static void nvic_sysreg_write(void *opaque, hwaddr addr, static void nvic_sysreg_write(void *opaque, hwaddr addr,
@ -418,7 +424,8 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr,
nvic_writel(s, offset, value); nvic_writel(s, offset, value);
return; return;
} }
hw_error("NVIC: Bad write of size %d at offset 0x%x\n", size, offset); qemu_log_mask(LOG_GUEST_ERROR,
"NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
} }
static const MemoryRegionOps nvic_sysreg_ops = { static const MemoryRegionOps nvic_sysreg_ops = {