Merge branch 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers. target-arm: Minimalistic CPU QOM'ification target-arm: Drop cpu_arm_close()
This commit is contained in:
commit
e7c56016f9
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@ -92,6 +92,7 @@ endif
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libobj-$(TARGET_SPARC64) += vis_helper.o
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libobj-$(CONFIG_NEED_MMU) += mmu.o
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libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
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libobj-$(TARGET_ARM) += cpu.o
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ifeq ($(TARGET_BASE_ARCH), sparc)
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libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
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libobj-y += cpu_init.o
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71
target-arm/cpu-qom.h
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71
target-arm/cpu-qom.h
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@ -0,0 +1,71 @@
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/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#ifndef QEMU_ARM_CPU_QOM_H
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#define QEMU_ARM_CPU_QOM_H
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#include "qemu/cpu.h"
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#include "cpu.h"
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#define TYPE_ARM_CPU "arm-cpu"
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#define ARM_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
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#define ARM_CPU(obj) \
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OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
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#define ARM_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
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/**
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* ARMCPUClass:
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* @parent_reset: The parent class' reset handler.
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*
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* An ARM CPU model.
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*/
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typedef struct ARMCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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void (*parent_reset)(CPUState *cpu);
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} ARMCPUClass;
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/**
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* ARMCPU:
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* @env: #CPUARMState
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*
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* An ARM CPU core.
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*/
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typedef struct ARMCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUARMState env;
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} ARMCPU;
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static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
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{
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return ARM_CPU(container_of(env, ARMCPU, env));
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}
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#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
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#endif
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60
target-arm/cpu.c
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60
target-arm/cpu.c
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@ -0,0 +1,60 @@
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/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "cpu-qom.h"
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#include "qemu-common.h"
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/* CPUClass::reset() */
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static void arm_cpu_reset(CPUState *s)
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{
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ARMCPU *cpu = ARM_CPU(s);
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
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acc->parent_reset(s);
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/* TODO Inline the current contents of cpu_state_reset(),
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once cpu_reset_model_id() is eliminated. */
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cpu_state_reset(&cpu->env);
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}
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static void arm_cpu_class_init(ObjectClass *oc, void *data)
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{
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ARMCPUClass *acc = ARM_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(acc);
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acc->parent_reset = cc->reset;
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cc->reset = arm_cpu_reset;
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}
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static const TypeInfo arm_cpu_type_info = {
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.name = TYPE_ARM_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(ARMCPU),
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.abstract = false,
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.class_size = sizeof(ARMCPUClass),
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.class_init = arm_cpu_class_init,
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};
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static void arm_cpu_register_types(void)
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{
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type_register_static(&arm_cpu_type_info);
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}
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type_init(arm_cpu_register_types)
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@ -238,7 +238,6 @@ typedef struct CPUARMState {
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CPUARMState *cpu_arm_init(const char *cpu_model);
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void arm_translate_init(void);
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int cpu_arm_exec(CPUARMState *s);
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void cpu_arm_close(CPUARMState *s);
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void do_interrupt(CPUARMState *);
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void switch_mode(CPUARMState *, int);
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uint32_t do_arm_semihosting(CPUARMState *env);
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@ -383,6 +382,7 @@ enum arm_features {
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ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
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ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
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ARM_FEATURE_GENERIC_TIMER,
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ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
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};
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static inline int arm_feature(CPUARMState *env, int feature)
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#endif
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#include "cpu-all.h"
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#include "cpu-qom.h"
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/* Bit usage in the TB flags field: */
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#define ARM_TBFLAG_THUMB_SHIFT 0
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@ -254,6 +254,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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}
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if (arm_feature(env, ARM_FEATURE_V6K)) {
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set_feature(env, ARM_FEATURE_V6);
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set_feature(env, ARM_FEATURE_MVFR);
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}
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if (arm_feature(env, ARM_FEATURE_V6)) {
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set_feature(env, ARM_FEATURE_V5);
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}
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}
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/* TODO Move contents into arm_cpu_reset() in cpu.c,
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* once cpu_reset_model_id() is eliminated,
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* and then forward to cpu_reset() here.
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*/
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void cpu_state_reset(CPUARMState *env)
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{
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uint32_t id;
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CPUARMState *cpu_arm_init(const char *cpu_model)
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{
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ARMCPU *cpu;
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CPUARMState *env;
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uint32_t id;
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static int inited = 0;
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id = cpu_arm_find_by_name(cpu_model);
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if (id == 0)
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return NULL;
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env = g_malloc0(sizeof(CPUARMState));
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cpu = ARM_CPU(object_new(TYPE_ARM_CPU));
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env = &cpu->env;
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cpu_exec_init(env);
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if (tcg_enabled() && !inited) {
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inited = 1;
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return id;
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}
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void cpu_arm_close(CPUARMState *env)
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{
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g_free(env);
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}
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static int bad_mode_switch(CPUARMState *env, int mode)
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{
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/* Return true if it is not valid for us to switch to
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@ -2906,7 +2906,7 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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case ARM_VFP_MVFR0:
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case ARM_VFP_MVFR1:
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if (IS_USER(s)
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|| !arm_feature(env, ARM_FEATURE_VFP3))
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|| !arm_feature(env, ARM_FEATURE_MVFR))
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return 1;
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tmp = load_cpu_field(vfp.xregs[rn]);
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break;
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