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target/ppc: Enable fp exceptions for user-only

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While just setting the MSR bits is sufficient, we can tidy
the helper code by extracting the MSR test to a helper and
then forcing it true for user-only.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson 2018-07-03 08:17:26 -07:00 committed by David Gibson
parent 1368898d4b
commit e82c42b7c5
2 changed files with 14 additions and 3 deletions
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15
target/ppc/fpu_helper.c
View file

@ -36,6 +36,15 @@ static inline float128 float128_snan_to_qnan(float128 x)
#define float32_snan_to_qnan(x) ((x) | 0x00400000) #define float32_snan_to_qnan(x) ((x) | 0x00400000)
#define float16_snan_to_qnan(x) ((x) | 0x0200) #define float16_snan_to_qnan(x) ((x) | 0x0200)
static inline bool fp_exceptions_enabled(CPUPPCState *env)
{
#ifdef CONFIG_USER_ONLY
return true;
#else
return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0;
#endif
}
/*****************************************************************************/ /*****************************************************************************/
/* Floating point operations helpers */ /* Floating point operations helpers */
uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg) uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
@ -207,7 +216,7 @@ uint64_t float_invalid_op_excp(CPUPPCState *env, int op, int set_fpcc)
if (ve != 0) { if (ve != 0) {
/* Update the floating-point enabled exception summary */ /* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX; env->fpscr |= 1 << FPSCR_FEX;
if (msr_fe0 != 0 || msr_fe1 != 0) { if (fp_exceptions_enabled(env)) {
/* GETPC() works here because this is inline */ /* GETPC() works here because this is inline */
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_FP | op, GETPC()); POWERPC_EXCP_FP | op, GETPC());
@ -225,7 +234,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
if (fpscr_ze != 0) { if (fpscr_ze != 0) {
/* Update the floating-point enabled exception summary */ /* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX; env->fpscr |= 1 << FPSCR_FEX;
if (msr_fe0 != 0 || msr_fe1 != 0) { if (fp_exceptions_enabled(env)) {
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX, POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX,
raddr); raddr);
@ -555,7 +564,7 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
if (cs->exception_index == POWERPC_EXCP_PROGRAM && if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
(env->error_code & POWERPC_EXCP_FP)) { (env->error_code & POWERPC_EXCP_FP)) {
/* Differred floating-point exception after target FPR update */ /* Differred floating-point exception after target FPR update */
if (msr_fe0 != 0 || msr_fe1 != 0) { if (fp_exceptions_enabled(env)) {
raise_exception_err_ra(env, cs->exception_index, raise_exception_err_ra(env, cs->exception_index,
env->error_code, raddr); env->error_code, raddr);
} }

2
target/ppc/translate_init.inc.c
View file

@ -10278,6 +10278,8 @@ static void ppc_cpu_reset(CPUState *s)
#endif #endif
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
msr |= (target_ulong)1 << MSR_FE1;
msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */