target/ppc: Enable fp exceptions for user-only
While just setting the MSR bits is sufficient, we can tidy the helper code by extracting the MSR test to a helper and then forcing it true for user-only. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -36,6 +36,15 @@ static inline float128 float128_snan_to_qnan(float128 x)
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#define float32_snan_to_qnan(x) ((x) | 0x00400000)
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#define float32_snan_to_qnan(x) ((x) | 0x00400000)
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#define float16_snan_to_qnan(x) ((x) | 0x0200)
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#define float16_snan_to_qnan(x) ((x) | 0x0200)
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static inline bool fp_exceptions_enabled(CPUPPCState *env)
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{
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#ifdef CONFIG_USER_ONLY
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return true;
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#else
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return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0;
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#endif
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}
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/*****************************************************************************/
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/*****************************************************************************/
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/* Floating point operations helpers */
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/* Floating point operations helpers */
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uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
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uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
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@ -207,7 +216,7 @@ uint64_t float_invalid_op_excp(CPUPPCState *env, int op, int set_fpcc)
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if (ve != 0) {
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if (ve != 0) {
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/* Update the floating-point enabled exception summary */
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/* Update the floating-point enabled exception summary */
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env->fpscr |= 1 << FPSCR_FEX;
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env->fpscr |= 1 << FPSCR_FEX;
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if (msr_fe0 != 0 || msr_fe1 != 0) {
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if (fp_exceptions_enabled(env)) {
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/* GETPC() works here because this is inline */
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/* GETPC() works here because this is inline */
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_FP | op, GETPC());
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POWERPC_EXCP_FP | op, GETPC());
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@ -225,7 +234,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
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if (fpscr_ze != 0) {
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if (fpscr_ze != 0) {
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/* Update the floating-point enabled exception summary */
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/* Update the floating-point enabled exception summary */
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env->fpscr |= 1 << FPSCR_FEX;
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env->fpscr |= 1 << FPSCR_FEX;
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if (msr_fe0 != 0 || msr_fe1 != 0) {
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if (fp_exceptions_enabled(env)) {
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX,
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POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX,
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raddr);
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raddr);
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@ -555,7 +564,7 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
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if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
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if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
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(env->error_code & POWERPC_EXCP_FP)) {
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(env->error_code & POWERPC_EXCP_FP)) {
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/* Differred floating-point exception after target FPR update */
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/* Differred floating-point exception after target FPR update */
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if (msr_fe0 != 0 || msr_fe1 != 0) {
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if (fp_exceptions_enabled(env)) {
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raise_exception_err_ra(env, cs->exception_index,
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raise_exception_err_ra(env, cs->exception_index,
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env->error_code, raddr);
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env->error_code, raddr);
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}
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}
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@ -10278,6 +10278,8 @@ static void ppc_cpu_reset(CPUState *s)
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#endif
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#endif
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#if defined(CONFIG_USER_ONLY)
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#if defined(CONFIG_USER_ONLY)
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msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
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msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
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msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
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msr |= (target_ulong)1 << MSR_FE1;
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msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
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msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
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msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
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msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
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msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
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msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
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