target/i386: Generate #UD when applying LOCK to a register destination
Fixes a TCG crash due to attempting the atomic operation without
having set up the address first. This does not attempt to fix
all of the other missing checks for LOCK.
Fixes: a7cee522f3
Fixes: https://bugs.launchpad.net/qemu/+bug/1803160
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20181113193510.24862-1-richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
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@ -1268,10 +1268,30 @@ static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
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}
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}
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static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
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{
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gen_update_cc_op(s);
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gen_jmp_im(s, cur_eip);
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gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
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s->base.is_jmp = DISAS_NORETURN;
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}
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/* Generate #UD for the current instruction. The assumption here is that
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the instruction is known, but it isn't allowed in the current cpu mode. */
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static void gen_illegal_opcode(DisasContext *s)
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{
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gen_exception(s, EXCP06_ILLOP, s->pc_start - s->cs_base);
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}
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/* if d == OR_TMP0, it means memory operand (address in A0) */
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static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
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{
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if (d != OR_TMP0) {
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if (s1->prefix & PREFIX_LOCK) {
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/* Lock prefix when destination is not memory. */
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gen_illegal_opcode(s1);
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return;
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}
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gen_op_mov_v_reg(s1, ot, s1->T0, d);
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} else if (!(s1->prefix & PREFIX_LOCK)) {
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gen_op_ld_v(s1, ot, s1->T0, s1->A0);
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@ -2469,21 +2489,6 @@ static void gen_leave(DisasContext *s)
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gen_op_mov_reg_v(s, a_ot, R_ESP, s->T1);
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}
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static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
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{
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gen_update_cc_op(s);
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gen_jmp_im(s, cur_eip);
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gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
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s->base.is_jmp = DISAS_NORETURN;
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}
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/* Generate #UD for the current instruction. The assumption here is that
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the instruction is known, but it isn't allowed in the current cpu mode. */
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static void gen_illegal_opcode(DisasContext *s)
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{
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gen_exception(s, EXCP06_ILLOP, s->pc_start - s->cs_base);
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}
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/* Similarly, except that the assumption here is that we don't decode
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the instruction at all -- either a missing opcode, an unimplemented
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feature, or just a bogus instruction stream. */
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